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| revision date: se p . 23 , 2005 16 h8/36087 group hardware manual rev.2.00 rej09b0160-0200 renesas 16-bit single-chip microcomputer h8 family/h8/300h tiny series h8/36087f hd64f36087 h8/36087 HD64336087 h8/36086 hd64336086 h8/36085 hd64336085 h8/36084 hd64336084 h8/36083 hd64336083 h8/36082 hd64336082
rev. 2.00 sep. 23, 2005 page ii of xxx rev. 2.00 sep. 23, 2005 page iii of xxx 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials rev. 2.00 sep. 23, 2005 page iv of xxx general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system?s operation is not guaranteed if they are accessed. rev. 2.00 sep. 23, 2005 page v of xxx configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index rev. 2.00 sep. 23, 2005 page vi of xxx preface the h8/36087 group are single-chip microcomputers made up of the high-speed h8/300h cpu employing renesas technology original architectur e as their cores, and th e peripheral functions required to configure a system. the h8/300h cpu ha s an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for user s who will be using the h8/36087 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of th e h8/36087 group to the target users. refer to the h8/300h series software ma nual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8/300h series software manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 22, list of registers. example: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. notes: when using an on-chip emulator (e7, e8) for h8/36087 program development and debugging, the following restrictions must be noted. rev. 2.00 sep. 23, 2005 page vii of xxx 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p87 cannot be used. in order to use these pins, additional hardware must be provided on the user board. 3. area h?d000 to h?dfff is used by the e7 or e8, and is not available to the user. 4. area h?f780 to h?fb7f must on no account be accessed. 5. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 6. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. 7. use channel 1 of the sci3 (p21/rxd, p22/txd) in on-board programming mode by boot mode. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ h8/36087 group manuals: document title document no. h8/36087 group hardware manual this manual h8/300h series software manual rej09b0213 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058 microcomputer development environment system h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series high-performance embedded workshop 3, tutorial rej10b0024 h8s, h8/300 series high-performance embedded workshop 3, user's manual rej10b0026 rev. 2.00 sep. 23, 2005 page viii of xxx application notes: document title document no. h8s, h8/300 series c/c++ compiler package application note rej05b0464 single power supply f-ztat tm on-board programming ade-502-055 rev. 2.00 sep. 23, 2005 page ix of xxx contents section 1 overview................................................................................................1 1.1 features....................................................................................................................... ........... 1 1.2 internal bloc k diagram......................................................................................................... .3 1.3 pin arrangement ................................................................................................................ .... 4 1.4 pin functions .................................................................................................................. ....... 5 section 2 cpu........................................................................................................9 2.1 address space and memory map ........................................................................................ 10 2.2 register conf igura tion......................................................................................................... 12 2.2.1 general registers.................................................................................................... 13 2.2.2 program counter (pc) ............................................................................................ 14 2.2.3 condition-code re gister (ccr)............................................................................. 14 2.3 data formats................................................................................................................... ..... 16 2.3.1 general register data formats ............................................................................... 16 2.3.2 memory data formats ............................................................................................ 18 2.4 instruction set ................................................................................................................ ...... 19 2.4.1 table of instructions cl assified by function .......................................................... 19 2.4.2 basic instructio n formats ....................................................................................... 29 2.5 addressing modes and effec tive address ca lculation........................................................ 30 2.5.1 addressing modes .................................................................................................. 30 2.5.2 effective address calculation ................................................................................ 34 2.6 basic bus cycle ................................................................................................................ ... 36 2.6.1 access to on-chip me mory (ram, rom)............................................................ 36 2.6.2 on-chip peripheral modules .................................................................................. 37 2.7 cpu states ..................................................................................................................... ...... 38 2.8 usage notes .................................................................................................................... ..... 39 2.8.1 notes on data acce ss to empty areas ................................................................... 39 2.8.2 eepmov instru ction.............................................................................................. 39 2.8.3 bit-manipulation instruction .................................................................................. 39 section 3 exception handling .............................................................................45 3.1 exception sources and vector address ............................................................................... 46 3.2 register de scriptions .......................................................................................................... .47 3.2.1 interrupt edge select register 1 (iegr1) .............................................................. 48 3.2.2 interrupt edge select register 2 (iegr2) .............................................................. 49 3.2.3 interrupt enable regi ster 1 (ienr1) ...................................................................... 50 rev. 2.00 sep. 23, 2005 page x of xxx 3.2.4 interrupt enable regi ster 2 (ienr2) ...................................................................... 51 3.2.5 interrupt flag register 1 (irr1)............................................................................. 51 3.2.6 interrupt flag register 2 (irr2)............................................................................. 53 3.2.7 wakeup interrupt flag register (iwpr) ................................................................ 53 3.3 reset exceptio n handling.................................................................................................... 55 3.4 interrupt exception handling .............................................................................................. 55 3.4.1 external interrupts .................................................................................................. 55 3.4.2 internal interrupts ................................................................................................... 57 3.4.3 interrupt handling sequence .................................................................................. 57 3.4.4 interrupt response time......................................................................................... 58 3.5 usage notes .................................................................................................................... ..... 60 3.5.1 interrupts after reset............................................................................................... 60 3.5.2 notes on stack area use ........................................................................................ 60 3.5.3 notes on rewriting port mode registers ............................................................... 60 section 4 address break ..................................................................................... 61 4.1 register de scriptions.......................................................................................................... .62 4.1.1 address break control register (a brkcr) ......................................................... 62 4.1.2 address break status register (a brksr) ............................................................ 64 4.1.3 break address register s (barh, barl).............................................................. 64 4.1.4 break data register s (bdrh, bdrl) ................................................................... 64 4.2 operation ...................................................................................................................... ....... 65 section 5 clock pulse generators ....................................................................... 67 5.1 system clock generator ...................................................................................................... 68 5.1.1 connecting crysta l resona tor ................................................................................ 68 5.1.2 connecting cerami c resonator .............................................................................. 69 5.1.3 external clock input method ................................................................................. 69 5.2 subclock generator............................................................................................................. .70 5.2.1 connecting 32.768-khz cr ystal resonator ............................................................ 70 5.2.2 pin connection when no t using subclock............................................................. 71 5.3 prescalers ..................................................................................................................... ........ 71 5.3.1 prescaler s .............................................................................................................. 71 5.3.2 prescaler w............................................................................................................. 71 5.4 usage notes .................................................................................................................... ..... 72 5.4.1 note on resonators................................................................................................. 72 5.4.2 notes on board design ........................................................................................... 72 rev. 2.00 sep. 23, 2005 page xi of xxx section 6 power-down modes ............................................................................73 6.1 register de scriptions .......................................................................................................... .74 6.1.1 system control regi ster 1 (syscr1) .................................................................... 74 6.1.2 system control regi ster 2 (syscr2) .................................................................... 76 6.1.3 module standby control register 1 (mstcr1) .................................................... 77 6.1.4 module standby control register 2 (mstcr2) .................................................... 78 6.2 mode transitions and states of lsi..................................................................................... 79 6.2.1 sleep mode ............................................................................................................. 82 6.2.2 standby mode......................................................................................................... 82 6.2.3 subsleep mode........................................................................................................ 82 6.2.4 subactive mode ...................................................................................................... 83 6.3 operating frequency in active mode.................................................................................. 83 6.4 direct tr ansition .............................................................................................................. .... 84 6.4.1 direct transition from activ e mode to subactive mode ....................................... 84 6.4.2 direct transition from subac tive mode to ac tive mode ....................................... 85 6.5 module standby function.................................................................................................... 85 section 7 rom ....................................................................................................87 7.1 block confi guratio n............................................................................................................ .87 7.2 register de scriptions .......................................................................................................... .89 7.2.1 flash memory control re gister 1 (flmcr1)........................................................ 89 7.2.2 flash memory control re gister 2 (flmcr2)........................................................ 90 7.2.3 erase block register 1 (ebr1) .............................................................................. 91 7.2.4 flash memory power contro l register (flpwcr) ............................................... 92 7.2.5 flash memory enable register (fenr) ................................................................. 92 7.3 on-board progra mming modes........................................................................................... 93 7.3.1 boot mode .............................................................................................................. 94 7.3.2 programming/erasing in user program mode........................................................ 96 7.4 flash memory prog ramming/erasing .................................................................................. 98 7.4.1 program/program-verify ........................................................................................ 98 7.4.2 erase/erase-verify................................................................................................ 101 7.4.3 interrupt handling when progra mming/erasing flash memory........................... 101 7.5 program/erase pr otection .................................................................................................. 103 7.5.1 hardware protection ............................................................................................. 103 7.5.2 software prot ection............................................................................................... 103 7.5.3 error protec tion..................................................................................................... 103 7.6 programmer mode ............................................................................................................. 104 7.7 power-down states fo r flash memory.............................................................................. 104 rev. 2.00 sep. 23, 2005 page xii of xxx section 8 ram .................................................................................................. 107 section 9 i/o ports............................................................................................. 109 9.1 port 1......................................................................................................................... ......... 109 9.1.1 port mode regist er 1 (pmr1) .............................................................................. 110 9.1.2 port control regist er 1 (pcr1) ............................................................................ 111 9.1.3 port data regist er 1 (pdr1) ................................................................................ 111 9.1.4 port pull-up control re gister 1 (pucr1)............................................................ 112 9.1.5 pin functio ns ........................................................................................................ 112 9.2 port 2......................................................................................................................... ......... 115 9.2.1 port control regist er 2 (pcr2) ............................................................................ 115 9.2.2 port data regist er 2 (pdr2) ................................................................................ 116 9.2.3 port mode regist er 3 (pmr3) .............................................................................. 116 9.2.4 pin functio ns ........................................................................................................ 117 9.3 port 3......................................................................................................................... ......... 118 9.3.1 port control regist er 3 (pcr3) ............................................................................ 119 9.3.2 port data regist er 3 (pdr3) ................................................................................ 119 9.3.3 pin functio ns ........................................................................................................ 120 9.4 port 5......................................................................................................................... ......... 122 9.4.1 port mode regist er 5 (pmr5) .............................................................................. 123 9.4.2 port control regist er 5 (pcr5) ............................................................................ 124 9.4.3 port data regist er 5 (pdr5) ................................................................................ 124 9.4.4 port pull-up control re gister 5 (pucr5)............................................................ 125 9.4.5 pin functio ns ........................................................................................................ 125 9.5 port 6......................................................................................................................... ......... 128 9.5.1 port control regist er 6 (pcr6) ............................................................................ 129 9.5.2 port data regist er 6 (pdr6) ................................................................................ 129 9.5.3 pin functio ns ........................................................................................................ 130 9.6 port 7......................................................................................................................... ......... 134 9.6.1 port control regist er 7 (pcr7) ............................................................................ 134 9.6.2 port data regist er 7 (pdr7) ................................................................................ 135 9.6.3 pin functio ns ........................................................................................................ 135 9.7 port 8......................................................................................................................... ......... 137 9.7.1 port control regist er 8 (pcr8) ............................................................................ 137 9.7.2 port data regist er 8 (pdr8) ................................................................................ 138 9.7.3 pin functio ns ........................................................................................................ 138 9.8 port b ......................................................................................................................... ........ 139 9.8.1 port data regist er b (pdrb) ............................................................................... 139 rev. 2.00 sep. 23, 2005 page xiii of xxx section 10 realtime clock (rtc) .....................................................................141 10.1 features....................................................................................................................... ....... 141 10.2 input/output pin............................................................................................................... .. 143 10.3 register desc riptions ......................................................................................................... 1 43 10.3.1 second data register/free running c ounter data register (rsecdr) ............. 143 10.3.2 minute data regist er (rmind r)......................................................................... 144 10.3.3 hour data regist er (rhrdr) .............................................................................. 145 10.3.4 day-of-week data regi ster (rwkdr) ............................................................... 146 10.3.5 rtc control register 1 (rtccr1)...................................................................... 147 10.3.6 rtc control register 2 (rtccr2)...................................................................... 148 10.3.7 clock source select re gister (rt ccsr) ............................................................. 149 10.4 operation ...................................................................................................................... ..... 150 10.4.1 initial settings of regist ers after po wer-on ......................................................... 150 10.4.2 initial setting pr ocedure ....................................................................................... 150 10.4.3 data reading pr ocedure ....................................................................................... 151 10.5 interrupt source ............................................................................................................... .. 152 section 11 timer b1 ..........................................................................................153 11.1 features....................................................................................................................... ....... 153 11.2 input/output pin............................................................................................................... .. 154 11.3 register desc riptions ......................................................................................................... 1 54 11.3.1 timer mode register b1 (tmb1) ........................................................................ 154 11.3.2 timer counter b1 (tcb1).................................................................................... 155 11.3.3 timer load register b1 (tlb1) .......................................................................... 155 11.4 operation ...................................................................................................................... ..... 156 11.4.1 interval timer operation ...................................................................................... 156 11.4.2 auto-reload timer operation .............................................................................. 156 11.4.3 event counter op eration ...................................................................................... 156 11.5 timer b1 operating modes ............................................................................................... 157 section 12 timer v............................................................................................159 12.1 features....................................................................................................................... ....... 159 12.2 input/output pins .............................................................................................................. .161 12.3 register desc riptions ......................................................................................................... 1 61 12.3.1 timer counter v (tcntv) .................................................................................. 161 12.3.2 time constant registers a and b (tcora, tcorb) ........................................ 162 12.3.3 timer control regist er v0 (t crv0) ................................................................... 162 12.3.4 timer control/status regi ster v (tcsrv) .......................................................... 164 12.3.5 timer control regist er v1 (t crv1) ................................................................... 165 rev. 2.00 sep. 23, 2005 page xiv of xxx 12.4 operation ...................................................................................................................... ..... 166 12.4.1 timer v operation................................................................................................ 166 12.5 timer v applicati on examples ......................................................................................... 169 12.5.1 pulse output with arb itrary duty cycle............................................................... 169 12.5.2 pulse output with arbitrary pulse wi dth and delay from trgv input .............. 170 12.6 usage notes .................................................................................................................... ... 171 section 13 timer z............................................................................................ 173 13.1 features....................................................................................................................... ....... 173 13.2 input/output pins.............................................................................................................. .178 13.3 register desc riptions......................................................................................................... 1 79 13.3.1 timer start regist er (tstr) ................................................................................ 180 13.3.2 timer mode regist er (tmdr)............................................................................. 180 13.3.3 timer pwm mode regi ster (tpmr) ................................................................... 181 13.3.4 timer function control register (t fcr) ............................................................ 182 13.3.5 timer output master enab le register (toer) .................................................... 185 13.3.6 timer output control register (t ocr)............................................................... 186 13.3.7 timer counter (tcnt)......................................................................................... 187 13.3.8 general registers a, b, c, and d (gra, grb, grc, and grd)........................ 188 13.3.9 timer control regi ster (tcr).............................................................................. 189 13.3.10 timer i/o control register (tiora and tiorc) ............................................... 190 13.3.11 timer status regi ster (tsr)................................................................................. 192 13.3.12 timer interrupt enable register (tier)............................................................... 194 13.3.13 pwm mode output level cont rol register (pocr) ........................................... 195 13.3.14 interface with cpu ............................................................................................... 196 13.4 operation ...................................................................................................................... ..... 197 13.4.1 counter operation ................................................................................................ 197 13.4.2 waveform output by compare ma tch.................................................................. 201 13.4.3 input capture function ......................................................................................... 204 13.4.4 synchronous op eration......................................................................................... 207 13.4.5 pwm mode .......................................................................................................... 209 13.4.6 reset synchronou s pwm mode........................................................................... 215 13.4.7 complementary pwm mode................................................................................ 219 13.4.8 buffer operation................................................................................................... 229 13.4.9 timer z output timing ........................................................................................ 236 13.5 interrupts..................................................................................................................... ....... 239 13.5.1 status flag se t timing.......................................................................................... 239 13.5.2 status flag clear ing timi ng ................................................................................. 241 13.6 usage notes .................................................................................................................... ... 242 rev. 2.00 sep. 23, 2005 page xv of xxx section 14 watchdog timer ..............................................................................251 14.1 features....................................................................................................................... ....... 251 14.2 register desc riptions ......................................................................................................... 2 52 14.2.1 timer control/status regi ster wd (t csrwd)................................................... 252 14.2.2 timer counter wd (tcwd)................................................................................ 253 14.2.3 timer mode register wd (tmwd) .................................................................... 254 14.3 operation ...................................................................................................................... ..... 255 section 15 14-bit pwm.....................................................................................257 15.1 features....................................................................................................................... ....... 257 15.2 input/output pin............................................................................................................... .. 258 15.3 register desc riptions ......................................................................................................... 2 58 15.3.1 pwm control regist er (pwcr) .......................................................................... 258 15.3.2 pwm data registers u an d l (pwdru, pwdrl)............................................. 259 15.4 operation ...................................................................................................................... ..... 259 section 16 serial communi cation interface 3 (sci3) .......................................261 16.1 features....................................................................................................................... ....... 261 16.2 input/output pins .............................................................................................................. .264 16.3 register desc riptions ......................................................................................................... 2 64 16.3.1 receive shift regi ster (rsr) ............................................................................... 265 16.3.2 receive data regi ster (rdr) ............................................................................... 265 16.3.3 transmit shift regist er tsr (sci3)..................................................................... 265 16.3.4 transmit data regi ster (tdr).............................................................................. 265 16.3.5 serial mode regi ster (smr) ................................................................................ 266 16.3.6 serial control regi ster 3 (scr3).......................................................................... 267 16.3.7 serial status regi ster (ssr) ................................................................................. 269 16.3.8 bit rate regist er (brr) ....................................................................................... 271 16.4 operation in asynch ronous mode ..................................................................................... 280 16.4.1 clock..................................................................................................................... 280 16.4.2 sci3 initiali zation................................................................................................. 281 16.4.3 data transmission ................................................................................................ 282 16.4.4 serial data reception ........................................................................................... 284 16.5 operation in clocked synchronous mode ......................................................................... 288 16.5.1 clock..................................................................................................................... 288 16.5.2 sci3 initiali zation................................................................................................. 288 16.5.3 serial data tr ansmission ...................................................................................... 289 16.5.4 serial data reception (clock ed synchronous mode)........................................... 292 16.5.5 simultaneous serial data tran smission and reception........................................ 294 16.6 multiprocessor co mmunication f unction.......................................................................... 296 rev. 2.00 sep. 23, 2005 page xvi of xxx 16.6.1 multiprocessor serial da ta transmission ............................................................. 298 16.6.2 multiprocessor serial data reception .................................................................. 300 16.7 interrupts..................................................................................................................... ....... 304 16.8 usage notes .................................................................................................................... ... 305 16.8.1 break detection an d processing ........................................................................... 305 16.8.2 mark state and br eak sending ............................................................................. 305 16.8.3 receive error flags and transmit operations (clocked synchronous mode only) ..................................................................... 305 16.8.4 receive data sampling timing and r eception margin in asynchronous mode..................................................................................................................... 306 section 17 i 2 c bus interface 2 (iic2)................................................................ 307 17.1 features....................................................................................................................... ....... 307 17.2 input/output pins.............................................................................................................. .310 17.3 register desc riptions......................................................................................................... 3 10 17.3.1 i 2 c bus control regist er 1 (iccr1 )..................................................................... 311 17.3.2 i 2 c bus control regist er 2 (iccr2 )..................................................................... 313 17.3.3 i 2 c bus mode regist er (icmr)............................................................................ 315 17.3.4 i 2 c bus interrupt enable register (i cier)........................................................... 317 17.3.5 i 2 c bus status regi ster (icsr)............................................................................. 319 17.3.6 slave address regi ster (sar).............................................................................. 322 17.3.7 i 2 c bus transmit data re gister (icdrt) ............................................................ 323 17.3.8 i 2 c bus receive data re gister (icd rr).............................................................. 323 17.3.9 i 2 c bus shift regist er (icdrs)............................................................................ 323 17.4 operation ...................................................................................................................... ..... 324 17.4.1 i 2 c bus format...................................................................................................... 324 17.4.2 master transmit operation................................................................................... 325 17.4.3 master receive operation .................................................................................... 327 17.4.4 slave transmit op eration ..................................................................................... 329 17.4.5 slave receive op eration....................................................................................... 332 17.4.6 clocked synchronous serial format .................................................................... 333 17.4.7 noise can celer...................................................................................................... 336 17.4.8 example of use..................................................................................................... 336 17.5 interrupt request.............................................................................................................. .. 341 17.6 bit synchronous circuit..................................................................................................... 342 17.7 usage notes .................................................................................................................... ... 343 17.7.1 issue (retransmission) of start/stop condi tions .................................................. 343 17.7.2 wait setting in i 2 c bus mode regist er (icmr) ................................................ 343 rev. 2.00 sep. 23, 2005 page xvii of xxx section 18 a/d converter..................................................................................345 18.1 features....................................................................................................................... ....... 345 18.2 input/output pins .............................................................................................................. .347 18.3 register desc riptions ......................................................................................................... 3 48 18.3.1 a/d data registers a to d (addra to addrd) .............................................. 348 18.3.2 a/d control/status re gister (adcsr) ................................................................ 349 18.3.3 a/d control regist er (adcr) ............................................................................. 350 18.4 operation ...................................................................................................................... ..... 351 18.4.1 single mode.......................................................................................................... 351 18.4.2 scan mode ............................................................................................................ 351 18.4.3 input sampling and a/d conversion time .......................................................... 352 18.4.4 external trigger input timi ng.............................................................................. 353 18.5 a/d conversion accura cy definitions .............................................................................. 354 18.6 usage notes .................................................................................................................... ... 356 18.6.1 permissible signal s ource impedance .................................................................. 356 18.6.2 influences on abso lute accuracy ......................................................................... 356 section 19 list of registers ...............................................................................357 19.1 register addresses (a ddress order).................................................................................. 358 19.2 register bits.................................................................................................................. ..... 364 19.3 registers states in ea ch operating mode.......................................................................... 369 section 20 electrica l characteristics .................................................................373 20.1 absolute maximum ratings .............................................................................................. 373 20.2 electrical characteristics (f-ztat? version)................................................................. 373 20.2.1 power supply voltage an d operating ranges ...................................................... 373 20.2.2 dc character istics ................................................................................................ 375 20.2.3 ac character istics ................................................................................................ 381 20.2.4 a/d converter char acteristic s .............................................................................. 385 20.2.5 watchdog timer ch aracteristic s........................................................................... 386 20.2.6 flash memory char acteristi cs .............................................................................. 387 20.3 electrical characteristics (mask-rom version) ............................................................... 389 20.3.1 power supply voltage an d operating ranges ...................................................... 389 20.3.2 dc character istics ................................................................................................ 391 20.3.3 ac character istics ................................................................................................ 397 20.3.4 a/d converter char acteristic s .............................................................................. 401 20.3.5 watchdog timer ch aracteristic s........................................................................... 402 20.4 operation timing............................................................................................................... 403 20.5 output load condition ...................................................................................................... 406 rev. 2.00 sep. 23, 2005 page xviii of xxx appendix a instruction set ............................................................................... 407 a.1 instruction list............................................................................................................... .... 407 a.2 operation code map.......................................................................................................... 422 a.3 number of execu tion stat es .............................................................................................. 425 a.4 combinations of instructions and addressing modes ....................................................... 437 appendix b i/o port block diagrams............................................................... 438 b.1 i/o port block diagrams ................................................................................................... 438 b.2 port states in each operating st ate ................................................................................... 460 appendix c product code lineup .................................................................... 461 appendix d package dimensions ..................................................................... 462 main revisions and additions in this edition..................................................... 465 index ......................................................................................................... 469 rev. 2.00 sep. 23, 2005 page xix of xxx figures section 1 overview figure 1.1 internal block diagram of h8/36087 group of f-ztat tm and mask-rom versions....................................................................................................................... .. 3 figure 1.2 pin arrangement of h8/36087 group of f-ztat tm and mask-rom versions (fp-64e, fp-64a).......................................................................................................... 4 section 2 cpu figure 2.1 memory map (1) .................................................................................................... ..... 10 figure 2.1 memory map (2) .................................................................................................... ..... 11 figure 2.2 cpu regi sters ..................................................................................................... ........ 12 figure 2.3 usage of general registers ........................................................................................ .13 figure 2.4 relationship between stack pointer an d stack area ................................................... 14 figure 2.5 general regi ster data formats (1).............................................................................. 16 figure 2.5 general regi ster data formats (2).............................................................................. 17 figure 2.6 memo ry data formats............................................................................................... .. 18 figure 2.7 inst ruction formats............................................................................................... ....... 29 figure 2.8 branch address specifi cation in memory indirect mode ........................................... 33 figure 2.9 on-chip memory acces s cycle.................................................................................. 36 figure 2.10 on-chip peripheral mo dule access cycle (3 -state access)..................................... 37 figure 2.11 cp u operation states............................................................................................. ... 38 figure 2.12 state tran siti ons ................................................................................................ ........ 39 figure 2.13 example of timer configuration with two registers allocated to same address...................................................................................................................... 40 section 3 exception handling figure 3.1 reset se quence.................................................................................................... ........ 56 figure 3.2 stack status after exceptio n handling ........................................................................ 58 figure 3.3 interrupt sequence................................................................................................ ....... 59 figure 3.4 port mode regi ster setting and interrupt reques t flag clearing procedure .............. 60 section 4 address break figure 4.1 block diag ram of address break................................................................................ 61 figure 4.2 address break inte rrupt operation example (1)......................................................... 65 figure 4.2 address break inte rrupt operation example (2)......................................................... 66 section 5 clock pulse generators figure 5.1 block diagram of clock pulse generators.................................................................. 67 figure 5.2 block diagram of system clock generator ................................................................ 68 figure 5.3 typical connect ion to crystal resonator.................................................................... 68 rev. 2.00 sep. 23, 2005 page xx of xxx figure 5.4 equivalent circ uit of crystal resonator...................................................................... 68 figure 5.5 typical connect ion to ceramic resonator.................................................................. 69 figure 5.6 example of external clock input ................................................................................ 69 figure 5.7 block diagram of subclock generator ....................................................................... 70 figure 5.8 typical connection to 32.768-khz crysta l resonator................................................ 70 figure 5.9 equivalent circuit of 32.768-khz crys tal resona tor.................................................. 70 figure 5.10 pin connectio n when not using subclock ................................................................ 71 figure 5.11 example of incorrect board design .......................................................................... 72 section 6 power-down modes figure 6.1 mode transition diagram ........................................................................................... 79 section 7 rom figure 7.1 flash memory block config uration............................................................................ 88 figure 7.2 programming/erasing flowch art example in user program mode............................ 97 figure 7.3 program/prog ram-verify flowchart ........................................................................... 99 figure 7.4 erase/eras e-verify flowchart ................................................................................... 102 section 9 i/o ports figure 9.1 port 1 pin config uration.......................................................................................... .. 109 figure 9.2 port 2 pin config uration.......................................................................................... .. 115 figure 9.3 port 3 pin config uration.......................................................................................... .. 118 figure 9.4 port 5 pin config uration.......................................................................................... .. 122 figure 9.5 port 6 pin config uration.......................................................................................... .. 128 figure 9.6 port 7 pin config uration.......................................................................................... .. 134 figure 9.7 port 8 pin config uration.......................................................................................... .. 137 figure 9.8 port b pin config uration.......................................................................................... .139 section 10 realtime clock (rtc) figure 10.1 bloc k diagram of rtc ........................................................................................... 14 2 figure 10.2 definition of time expr ession ................................................................................ 147 figure 10.3 initia l setting procedure........................................................................................ .. 150 figure 10.4 example: readin g of inaccurate time data............................................................ 151 section 11 timer b1 figure 11.1 block di agram of timer b1.................................................................................... 153 section 12 timer v figure 12.1 block di agram of timer v ..................................................................................... 160 figure 12.2 increment timi ng with intern al clock .................................................................... 167 figure 12.3 increment timi ng with extern al clock................................................................... 167 figure 12.4 ovf set timing ................................................................................................... ... 167 figure 12.5 cmfa an d cmfb set timing................................................................................ 168 rev. 2.00 sep. 23, 2005 page xxi of xxx figure 12.6 tmov output timing ............................................................................................ 168 figure 12.7 clear timi ng by compare match............................................................................ 168 figure 12.8 clear ti ming by tmriv input ............................................................................... 169 figure 12.9 pulse output example ............................................................................................. 169 figure 12.10 example of pulse outp ut synchronized to trgv input....................................... 170 figure 12.11 contention betw een tcntv write and clear ...................................................... 171 figure 12.12 contention between tcora write and co mpare match ..................................... 172 figure 12.13 internal clock sw itching and tcntv operation ................................................. 172 section 13 timer z figure 13.1 time r z block di agram .......................................................................................... 17 5 figure 13.2 timer z (cha nnel 0) block diagram ...................................................................... 176 figure 13.3 timer z (cha nnel 1) block diagram ...................................................................... 177 figure 13.4 example of outputs in reset synchronous pwm mode and complementary pwm mode ............................................................................................................. 184 figure 13.5 accessing operation of 16-bit re gister (between cpu and tcnt (16 bits)) ........ 196 figure 13.6 accessing operation of 8-bit re gister (between cpu and tstr (8 bits))............. 196 figure 13.7 example of counte r operation setting procedure .................................................. 197 figure 13.8 free-runnin g counter operation ............................................................................ 198 figure 13.9 periodic counter operation..................................................................................... 19 9 figure 13.10 count timing at internal clock operation............................................................ 199 figure 13.11 count timing at external clock operation (both edges detected)...................... 200 figure 13.12 example of setting procedure for waveform output by compare match............ 201 figure 13.13 example of 0 ou tput/1 output operation ............................................................. 202 figure 13.14 example of toggle output op eration ................................................................... 203 figure 13.15 output compare timing........................................................................................ 204 figure 13.16 example of input ca pture operation setti ng procedure ....................................... 205 figure 13.17 example of input capture op eration..................................................................... 206 figure 13.18 input ca pture signal timing ................................................................................. 207 figure 13.19 example of synchro nous operation settin g procedure ........................................ 208 figure 13.20 example of synchronous op eration...................................................................... 209 figure 13.21 example of pw m mode setting pr ocedure .......................................................... 210 figure 13.22 example of pwm mode opera tion (1) ................................................................. 211 figure 13.23 example of pwm mode opera tion (2) ................................................................. 212 figure 13.24 example of pwm mode opera tion (3) ................................................................. 213 figure 13.25 example of pwm mode opera tion (4) ................................................................. 214 figure 13.26 example of reset sync hronous pwm mode setting procedure........................... 216 figure 13.27 example of reset synchronous pwm mode operation (ols0 = ols1 = 1) ...... 217 figure 13.28 example of reset synchronous pwm mode operation (ols0 = ols1 = 0) ...... 218 figure 13.29 example of complement ar y pwm mode setting procedure............................... 220 figure 13.30 canceling procedur e of complementary pwm mode .......................................... 221 rev. 2.00 sep. 23, 2005 page xxii of xxx figure 13.31 example of compleme ntary pwm mode op eration (1) ...................................... 222 figure 13.32 (1) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 = 0) (2) ................................................................ 224 figure 13.32 (2) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 0) (3) ................................................................ 225 figure 13.33 timi ng of overshooting ........................................................................................ 22 6 figure 13.34 timing of undershoo ting ...................................................................................... 226 figure 13.35 compare ma tch buffer operation......................................................................... 229 figure 13.36 input capt ure buffer op eration............................................................................. 230 figure 13.37 example of buffe r operation setting procedure................................................... 230 figure 13.38 example of buffer operation (1) (buffer operation for output compare register) ................................................. 231 figure 13.39 example of compare ma tch timing for buffer operation ................................... 232 figure 13.40 example of buffer operation (2) (buffer operation for inpu t capture regi ster) ...................................................... 233 figure 13.41 input capture timing of buffer operation............................................................ 234 figure 13.42 buff er operation (3) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1)............ 235 figure 13.43 buff er operation (4) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1)............ 236 figure 13.44 example of output disabl e timing of timer z by writing to toer .................. 237 figure 13.45 example of output disable timing of timer z by ex ternal trigger.................... 237 figure 13.46 example of output invers e timing of timer z by writing to tfcr ................... 238 figure 13.47 example of output invers e timing of timer z by writing to pocr................... 238 figure 13.48 imf flag set timi ng when compare match occurs ............................................ 239 figure 13.49 imf flag set timing at input capture .................................................................. 240 figure 13.50 ovf flag set timing ............................................................................................ 2 40 figure 13.51 status flag clearing timing.................................................................................. 241 figure 13.52 contention between tc nt write and clear operations....................................... 242 figure 13.53 contention between tcnt write and increment operations ............................... 243 figure 13.54 contention between gr write and comp are match............................................. 244 figure 13.55 contention between tcnt write an d overfl ow................................................... 245 figure 13.56 contention between gr read and inpu t capture.................................................. 246 figure 13.57 contention between count clearing and increment operations by input capture .................................................................................................................. 247 figure 13.58 contention between gr write and inpu t capture................................................. 248 figure 13.59 when compare match and bit manipulation instruction to tocr occur at the same timing ......................................................................................................... 250 rev. 2.00 sep. 23, 2005 page xxiii of xxx section 14 watchdog timer figure 14.1 block diagra m of watchdog timer ........................................................................ 251 figure 14.2 watchdog ti mer operation example...................................................................... 255 section 15 14-bit pwm figure 15.1 block di agram of 14-b it pwm .............................................................................. 257 figure 15.2 waveform output by 14 -bit pwm ......................................................................... 260 section 16 serial commu nication interface 3 (sci3) figure 16.1 bloc k diagram of sci3 ........................................................................................... 2 63 figure 16.2 data format in asynchronous co mmunication ...................................................... 280 figure 16.3 relationship between output clock and transfer data phase (asynchronous mode)(example with 8-bit data, parity, two stop bits) .............. 280 figure 16.4 sample sci3 initialization fl owchart ..................................................................... 281 figure 16.5 example of sci3 transmission in asynchronous mode (8-bit data, parity, one stop bit) ........................................................................... 282 figure 16.6 sample serial transmissi on data flowchart (asynchronous mode)...................... 283 figure 16.7 example of sci3 reception in asynchronous mode (8-bit data, parity, one stop bit) ........................................................................... 284 figure 16.8 sample serial reception da ta flowchart (asynchr onous mode)(1)....................... 286 figure 16.8 sample serial reception da ta flowchart (asynchr onous mode)(2)....................... 287 figure 16.9 data format in cl ocked synchronous communication .......................................... 288 figure 16.10 example of sci3 transm ission in clocked sy nchronous mode........................... 290 figure 16.11 sample serial transmission flowchart (clocked sy nchronous mode) ................ 291 figure 16.12 example of sci3 recep tion in clocked sync hronous mode................................ 292 figure 16.13 sample serial reception fl owchart (clocked synchronous mode)...................... 293 figure 16.14 sample flowchart of simultaneous serial transmit and receive operations (clocked synchronous mode)............................................................................... 295 figure 16.15 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving st ation a) .......................................... 297 figure 16.16 sample multiprocessor serial transmissi on flowchart ........................................ 299 figure 16.17 sample multiprocessor serial reception fl owchart (1)........................................ 301 figure 16.17 sample multiprocessor serial reception fl owchart (2)........................................ 302 figure 16.18 example of sci3 reception us ing multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit) ............................................................... 303 figure 16.19 receive data sampli ng timing in asynchronous mode ...................................... 306 section 17 i 2 c bus interface 2 (iic2) figure 17.1 block diagram of i 2 c bus interf ace 2..................................................................... 308 figure 17.2 external circu it connections of i/o pins ................................................................ 309 figure 17.3 i 2 c bus form ats ...................................................................................................... 324 rev. 2.00 sep. 23, 2005 page xxiv of xxx figure 17.4 i 2 c bus timi ng........................................................................................................ 324 figure 17.5 master transmit mode operation timing (1)......................................................... 326 figure 17.6 master transmit mode operation timing (2)......................................................... 326 figure 17.7 master receive mode operation timing (1) .......................................................... 328 figure 17.8 master receive mode operation timing (2) .......................................................... 329 figure 17.9 slave transmit mode operation timing (1) ........................................................... 330 figure 17.10 slave transmit mode operation timing (2) ......................................................... 331 figure 17.11 slave receive mode operation timing (1)........................................................... 332 figure 17.12 slave receive mode operation timing (2)........................................................... 333 figure 17.13 clocked synchron ous serial transfer format....................................................... 333 figure 17.14 transmit mode operatio n timing......................................................................... 334 figure 17.15 receive mo de operation timing .......................................................................... 335 figure 17.16 block diag ram of noise conceler ........................................................................ 336 figure 17.17 sample flowchar t for master tr ansmit mode ...................................................... 337 figure 17.18 sample flowchar t for master r eceive mode ........................................................ 338 figure 17.19 sample flowchar t for slave tran smit mode......................................................... 339 figure 17.20 sample flowch art for slave r eceive mode .......................................................... 340 figure 17.21 the timing of th e bit synchronou s circuit .......................................................... 342 section 18 a/d converter figure 18.1 block diag ram of a/d c onverter ........................................................................... 346 figure 18.2 a/d conversion timing.......................................................................................... 35 2 figure 18.3 external trigger input timing ................................................................................ 353 figure 18.4 a/d conversion accuracy definitions (1).............................................................. 355 figure 18.5 a/d conversion accuracy definitions (2).............................................................. 355 figure 18.6 analog i nput circuit ex ample ................................................................................ 356 section 20 electrical characteristics figure 20.1 system clock input timing .................................................................................... 403 figure 20.2 res low width timing.......................................................................................... 403 figure 20.3 input timing..................................................................................................... ....... 403 figure 20.4 i 2 c bus interface inpu t/output ti ming ................................................................... 404 figure 20.5 sck3 input clock timing ...................................................................................... 404 figure 20.6 sci input/output timi ng in clocked synchronous mode ...................................... 405 figure 20.7 outp ut load circuit .............................................................................................. .. 406 appendix figure b.1 port 1 block diagra m (p17) ..................................................................................... 438 figure b.2 port 1 bloc k diagram (p14, p16) ............................................................................. 439 figure b.3 port 1 block diagra m (p15) ..................................................................................... 440 figure b.4 port 1 block diagra m (p12) ..................................................................................... 441 figure b.5 port 2 block diagra m (p11) ..................................................................................... 442 rev. 2.00 sep. 23, 2005 page xxv of xxx figure b.6 port 1 block diagra m (p10) ..................................................................................... 443 figure b.7 port 2 bloc k diagram (p24, p23) ............................................................................. 444 figure b.8 port 2 block diagra m (p22) ..................................................................................... 445 figure b.9 port 2 block diagra m (p21) ..................................................................................... 446 figure b.10 port 2 block diagram (p20) ................................................................................... 447 figure b.11 port 3 bloc k diagram (p37 to p30) ........................................................................ 448 figure b.12 port 5 bl ock diagram (p57, p56) ........................................................................... 449 figure b.13 port 5 block diagram (p55) ................................................................................... 450 figure b.14 port 5 bloc k diagram (p54 to p50) ........................................................................ 451 figure b.15 port 6 bloc k diagram (p67 to p60) ........................................................................ 452 figure b.16 port 7 block diagram (p76) ................................................................................... 453 figure b.17 port 7 block diagram (p75) ................................................................................... 454 figure b.18 port 7 block diagram (p74) ................................................................................... 455 figure b.19 port 7 block diagram (p72) ................................................................................... 456 figure b.20 port 7 block diagram (p71) ................................................................................... 457 figure b.21 port 7 block diagram (p70) ................................................................................... 457 figure b.22 port 8 bloc k diagram (p87 to p85) ........................................................................ 458 figure b.23 port b bloc k diagram (pb7 to pb0) ...................................................................... 459 figure d.1 fp-64e package dimensions.................................................................................... 463 figure d.2 fp-64a package dimensions ................................................................................... 464 rev. 2.00 sep. 23, 2005 page xxvi of xxx rev. 2.00 sep. 23, 2005 page xxvii of xxx tables section 1 overview table 1.1 pin functions ............................................................................................................ 5 section 2 cpu table 2.1 operation notation ................................................................................................. 19 table 2.2 data transfer instructions....................................................................................... 20 table 2.3 arithmetic operations instructions (1) ................................................................... 21 table 2.3 arithmetic operations instructions (2) ................................................................... 22 table 2.4 logic operations instructions................................................................................. 23 table 2.5 shift instru ctions..................................................................................................... 23 table 2.6 bit manipulation inst ructions (1)............................................................................ 24 table 2.6 bit manipulation inst ructions (2)............................................................................ 25 table 2.7 branch instructions ................................................................................................. 26 table 2.8 system control instructions.................................................................................... 27 table 2.9 block data transfer instructions ............................................................................ 28 table 2.10 addressing modes .................................................................................................. 30 table 2.11 absolute address access ranges ........................................................................... 32 table 2.12 effective address ca lculation (1)........................................................................... 34 table 2.12 effective address ca lculation (2)........................................................................... 35 section 3 exception handling table 3.1 exception sources and vector address .................................................................. 46 table 3.2 interrupt wa it states ............................................................................................... 58 section 4 address break table 4.1 access and data bus used ..................................................................................... 63 section 5 clock pulse generators table 5.1 crystal resonato r parameters ................................................................................. 69 section 6 power-down modes table 6.1 operating frequency and waiting time................................................................. 75 table 6.2 transition mode after sleep instruction execution and transition mode due to interrupt .................................................................................................................. 80 table 6.3 internal state in ea ch operating mode................................................................... 81 section 7 rom table 7.1 setting programming modes .................................................................................. 93 table 7.2 boot mode operation ............................................................................................. 95 rev. 2.00 sep. 23, 2005 page xxviii of xxx table 7.3 system clock frequencies for which automa tic adjustment of lsi bit rate is possible................................................................................................................... 96 table 7.4 reprogram data com putation table .................................................................... 100 table 7.5 additional-program data computation table ...................................................... 100 table 7.6 programming time ............................................................................................... 100 table 7.7 flash memory oper ating states............................................................................ 105 section 10 realtime clock (rtc) table 10.1 pin configuration.................................................................................................. 143 table 10.2 interrupt source .................................................................................................... 152 section 11 timer b1 table 11.1 pin configuration.................................................................................................. 154 table 11.2 timer b1 operating modes .................................................................................. 157 section 12 timer v table 12.1 pin configuration.................................................................................................. 161 table 12.2 clock signals to input to tc ntv and counting conditions ............................... 163 section 13 timer z table 13.1 timer z functions ................................................................................................ 174 table 13.2 pin configuration.................................................................................................. 178 table 13.3 initial output level of ftiob0 pin...................................................................... 210 table 13.4 output pins in reset sy nchronous pwm mode................................................... 215 table 13.5 register settings in reset synchronous pw m mode........................................... 215 table 13.6 output pins in complementary pwm mode........................................................ 219 table 13.7 register settings in comp lementary pw m mode................................................ 219 table 13.8 register combinations in buffer operation ......................................................... 229 section 15 14-bit pwm table 15.1 pin configuration.................................................................................................. 258 section 16 serial commu nication interface 3 (sci3) table 16.1 channel config uration.......................................................................................... 262 table 16.2 pin configuration.................................................................................................. 264 table 16.3 examples of brr settings for various b it rates (asynchronous mode) (1) ...... 272 table 16.3 examples of brr settings for various b it rates (asynchronous mode) (2) ...... 273 table 16.3 examples of brr settings for various b it rates (asynchronous mode) (3) ...... 275 table 16.4 maximum bit rate for each fre quency (asynchronous mode) .......................... 277 table 16.5 examples of brr settings for various bit rates (clocked synchronous mode) (1) ......................................................................................................................... 278 table 16.5 examples of brr settings for various bit rates (clocked synchronous mode) (2) ......................................................................................................................... 279 rev. 2.00 sep. 23, 2005 page xxix of xxx table 16.6 ssr status flags and recei ve data ha ndling ...................................................... 285 table 16.7 sci3 interrupt requests........................................................................................ 304 section 17 i 2 c bus interface 2 (iic2) table 17.1 i 2 c bus interface pins........................................................................................... 310 table 17.2 transfer rate ........................................................................................................ 312 table 17.3 interrupt re quests ................................................................................................. 341 table 17.4 time for monitoring scl..................................................................................... 342 section 18 a/d converter table 18.1 pin configuration.................................................................................................. 347 table 18.2 analog input channels and corr esponding addr registers .............................. 348 table 18.3 a/d conversion time (single mode)................................................................... 353 section 20 electrical characteristics table 20.1 absolute maximum ratings ................................................................................. 373 table 20.2 dc characteris tics (1)........................................................................................... 375 table 20.2 dc characteris tics (2)........................................................................................... 380 table 20.3 ac character istics ................................................................................................ 381 table 20.4 i 2 c bus interface timing ...................................................................................... 383 table 20.5 serial communication inte rface (sci) timing..................................................... 384 table 20.6 a/d converter char acteristic s .............................................................................. 385 table 20.7 watchdog timer ch aracteristic s........................................................................... 386 table 20.8 flash memory char acteristic s .............................................................................. 387 table 20.9 dc characteris tics (1)........................................................................................... 391 table 20.9 dc characteris tics (2)........................................................................................... 396 table 20.10 ac character istics ............................................................................................ 397 table 20.11 i 2 c bus interface timing .................................................................................. 399 table 20.12 serial communication inte rface (sci) timing................................................. 400 table 20.13 a/d converter char acteristic s .......................................................................... 401 table 20.14 watchdog timer ch aracteristic s....................................................................... 402 appendix table a.1 instruction set ....................................................................................................... 409 table a.2 operation code map (1) ....................................................................................... 422 table a.2 operation code map (2) ....................................................................................... 423 table a.2 operation code map (3) ....................................................................................... 424 table a.3 number of cycles in each instruction.................................................................. 426 table a.4 number of cycles in each instruction.................................................................. 427 table a.5 combinations of instructions and addressing modes .......................................... 437 rev. 2.00 sep. 23, 2005 page xxx of xxx section 1 overview rev. 2.00 sep. 23, 2005 page 1 of 472 rej09b0160-0200 section 1 overview 1.1 features ? high-speed h8/300h central processing un it with an internal 16-bit architecture ? upward-compatible with h8/300 cpu on an object level ? sixteen 16-bit general registers ? 62 basic instructions ? various peripheral functions ? rtc (can be used as a free running counter) ? timer b1 (8-bit timer) ? timer v (8-bit timer) ? timer z (16-bit timer) ? 14-bit pwm ? watchdog timer ? sci (asynchronous or clocked synchronous serial communication interface) 2 channels ? i 2 c bus interface (conforms to the i 2 c bus interface format that is advocated by philips electronics) ? 10-bit a/d converter section 1 overview rev. 2.00 sep. 23, 2005 page 2 of 472 rej09b0160-0200 ? on-chip memory model product classification standard version rom ram remarks flash memory version (f-ztat tm version) h8/36087f hd64f36087 56 kbytes 4 kbytes h8/36087 HD64336087 56 kbytes 3 kbytes h8/36086 hd64336086 48 kbytes 3 kbytes h8/36085 hd64336085 40 kbytes 3 kbytes h8/36084 hd64336084 32 kbytes 3 kbytes h8/36083 hd64336083 24 kbytes 3 kbytes mask-rom version h8/36082 hd64336082 16 kbytes 3 kbytes ? general i/o ports ? i/o pins: 45 i/o pins including 8 large current ports (i ol = 10 ma, @v ol = 1.0v) ? input-only pins: 8 input pins (also used for analog input) ? supports various power-down states note: f-ztat tm is a trademark of renesas technology corp. ? compact package package code body size pin pitch lqfp-64 fp-64e 10.0 10.0 mm 0.5 mm qfp-64 fp-64a 14.0 14.0 mm 0.8 mm section 1 overview rev. 2.00 sep. 23, 2005 page 3 of 472 rej09b0160-0200 1.2 internal block diagram p10/tmow p11/pwm p12 p14/ irq0 p15/ irq1 /tmib1 p16/ irq2 p17/ irq3 /trgv p57/scl p56/sda p55/ wkp5 / adtrg p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 v cc v cc v ss res test nmi av cc p20/sck3 p21/rxd p22/txd p23 p24 p87 p86 p85 osc1 osc2 x1 x2 cpu h8/300h data bus (lower) system clock generator subclock generator rom 14-bit pwm timer z timer v a/d converter ram rtc sci3 sci3_2 watchdog timer iic2 p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 p60/ftioa0 p76/tmov p75/tmciv p74/tmriv p72/txd_2 p71/rxd_2 p70/sck3_2 p30 p31 p32 p33 p34 p35 p36 p37 data bus (upper) address bus port b port 8 port 7 port 6 port 1 port 2 port 3 port 5 timer b1 figure 1.1 internal block diagram of h8/36087 group of f-ztat tm and mask-rom versions section 1 overview rev. 2.00 sep. 23, 2005 page 4 of 472 rej09b0160-0200 1.3 pin arrangement pb6/an6 pb7/an7 avcc x2 x1 vcc res test vss osc2 osc1 vcc p50/ wkp0 p51/ wkp1 p34 p35 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p70/sck3_2 p23 p22/txd p21/rxd p20/sck3 p87 p86 p85 p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p60/ftioa0 nmi p61/ftiob0 p62/ftioc0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p71/rxd_2 p72/txd_2 p14/ irq0 p15/ irq1 /tmib1 p16/ irq2 p17/ irq3 /trgv p33 p32 p31 p30 pb3/an3 pb2/an2 pb1/an1 pb0/an0 pb4/an4 pb5/an5 p63/ftiod0 p24 p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda p12 p11/pwm p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 p37 p36 h8/36087 group top view figure 1.2 pin arrangement of h8/36087 group of f-ztat tm and mask-rom versions (fp-64e, fp-64a) section 1 overview rev. 2.00 sep. 23, 2005 page 5 of 472 rej09b0160-0200 1.4 pin functions table 1.1 pin functions pin no. type symbol fp-64e fp-64a i/o functions power source pins v cc 6, 12 input power supply pin. be sure to connect both two pins to the system power supply. v ss 9 input ground pin. connect this pin to the system power supply (0v). av cc 3 input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. clock pins osc1 11 input osc2 10 output these pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. see section 5, clock pulse generators, for a typical connection. x1 5 input x2 4 output these pins connect with a 32.768 khz crystal resonator for the subclock. see section 5, clock pulse generators, for a typical connection. system control res 7 input reset pin. the pull-up resistor (typ. 150 k ? ) is incorporated. when driven low, the chip is reset. test 8 input test pin. connect this pin to vss. nmi 35 input non-maskable interrupt request input pin. be sure to pull-up by a pull-up resistor. interrupt pins irq0 to irq3 51 to 54 input external interrupt request input pins. can select the rising or falling edge. wkp0 to wkp5 13, 14, 19 to 22 input external interrupt request input pins. can select the rising or falling edge. rtc tmow 23 output this is an output pin for divided clocks. timer b1 tmib1 52 input external event input pin. timer v tmov 30 output this is an output pin for waveforms generated by the output compare function. tmciv 29 input external event input pin. tmriv 28 input counter reset input pin. trgv 54 input counter start trigger input pin. section 1 overview rev. 2.00 sep. 23, 2005 page 6 of 472 rej09b0160-0200 pin no. type symbol fp-64e fp-64a i/o functions timer z ftioa0 36 i/o output co mpare output/in put capture input/external clock input pin ftiob0 34 i/o output com pare output/in put capture input/pwm output pin ftioc0 33 i/o output com pare output/in put capture input/pwm sync output pin (at a reset, complementary pwm mode) ftiod0 32 i/o output com pare output/in put capture input/pwm output pin ftioa1 37 i/o output com pare output/in put capture input/pwm output pin (at a reset, complementary pwm mode) ftiob1 to ftiod1 38 to 40 i/o output compar e output/input capture input/pwm output pin 14-bit pwm pwm 24 output 14-bit pwm square wave output pin i 2 c bus interface (iic) sda 26 i/o iic data i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistance is required. scl 27 i/o iic clock i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistance is required. txd, txd_2 46, 50 output trans mit data output pin serial com- munication interface (sci) rxd, rxd_2 45, 49 input receive data input pin sck3, sck3_2 44, 48 i/o clock i/o pin a/d converter an7 to an0 1, 2, 59 to 64 input analog input pin adtrg 22 input a/d converter trigger input pin. section 1 overview rev. 2.00 sep. 23, 2005 page 7 of 472 rej09b0160-0200 pin no. type symbol fp-64e fp-64a i/o functions i/o ports pb7 to pb0 1, 2, 59 to 64 input 8-bit input port. p17 to p14, p12 to p10 51 to 54, 23 to 25 i/o 7-bit i/o port. p24 to p20 31, 44 to 47 i/o 5-bit i/o port. p37 to p30 15 to 18, 55 to 58 i/o 8-bit i/o port p57 to p50 13, 14, 19 to 22, 26, 27 i/o 8-bit i/o port p67 to p60 32 to 34, 36, 37 to 40 i/o 8-bit i/o port p76 to p74, p72 to p70 28 to 30, 48 to 50 i/o 6-bit i/o port p87 to p85 41 to 43 i/o 3-bit i/o port. section 1 overview rev. 2.00 sep. 23, 2005 page 8 of 472 rej09b0160-0200 section 2 cpu cpu30h2c_000120030300 rev. 2.00 sep. 23, 2005 page 9 of 472 rej09b0160-0200 section 2 cpu this lsi has an h8/300h cpu with an internal 32-bit architecture that is upward-compatible with the h8/300cpu, and supports only normal mode, which has a 64-kbyte address space. ? upward-compatible with h8/300 cpus ? can execute h8/300 cpus object programs ? additional eight 16-bit extended registers ? 32-bit transfer and arithmetic an d logic instructions are added ? signed multiply and divide instructions are added. ? general-register architecture ? sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers ? sixty-two basic instructions ? 8/16/32-bit data transfer and arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:24,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @?ern] ? absolute address [@aa: 8, @aa:16, @aa:24] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 64-kbyte address space ? high-speed operation ? all frequently-used instructions execute in one or two states ? 8/16/32-bit register-register add/subtract : 2 state ? 8 8-bit register-register multiply : 14 states ? 16 8-bit register-regist er divide : 14 states ? 16 16-bit register-register multiply : 22 states ? 32 16-bit register-regist er divide : 22 states section 2 cpu rev. 2.00 sep. 23, 2005 page 10 of 472 rej09b0160-0200 ? power-down state ? transition to power-down state by sleep instruction 2.1 address space and memory map the address space of this lsi is 64 kbytes, which includes th e program area and the data area. figures 2.1 show the memory map. h'0000 h'0041 h'0042 h'dfff h'fb7f h'ff7f h'ff80 h'fb80 h'f77f h'f780 h'f700 h'efff h'e800 h'ffff hd64f36087 (flash memory version) interrupt vector on-chip rom (56 kbytes) internal i/o register internal i/o register (1 kbyte work area for flash memory programming) (1 kbyte user area) on-chip ram (2 kbytes) on-chip ram (2 kbytes) not used not used h'fb80 h'f77f h'f700 h'efff h'e800 hd64336082 (mask-rom version) h'0000 h'0041 h'0042 h'ff7f h'ff80 h'ffff h'3fff interrupt vector internal i/o register internal i/o register on-chip rom (16 kbytes) on-chip ram (2 kbytes) on-chip ram (1 kbytes) not used not used not used h'fb80 h'f77f h'f700 h'efff h'e800 hd64336083 (mask-rom version) h'0000 h'0041 h'0042 h'ff7f h'ff80 h'ffff h'5fff interrupt vector internal i/o register internal i/o register on-chip rom (24 kbytes) on-chip ram (2 kbytes) on-chip ram (1 kbytes) not used not used not used figure 2.1 memory map (1) section 2 cpu rev. 2.00 sep. 23, 2005 page 11 of 472 rej09b0160-0200 h'0000 h'0041 h'0042 h'bfff h'ff7f h'ff80 h'ffff HD64336087 (mask-rom version) hd64336086 (mask-rom version) h'0000 h'0041 h'0042 h'dfff h'ff7f h'ff80 h'ffff h'fb80 h'f77f h'f700 h'efff h'e800 h'fb80 h'f77f h'f700 h'efff h'e800 h'fb80 h'f77f h'f700 h'efff h'e800 hd64336085 (mask-rom version) h'0000 h'0041 h'0042 h'ff7f h'ff80 h'ffff h'9fff interrupt vector interrupt vector interrupt vector on-chip rom (40 kbytes) on-chip ram (2 kbytes) on-chip ram (1 kbytes) not used interrupt vector on-chip rom (48 kbytes) not used interrupt vector on-chip rom (56 kbytes) not used not used not used interrupt vector interrupt vector on-chip ram (2 kbytes) on-chip ram (1 kbytes) not used not used interrupt vector interrupt vector on-chip ram (2 kbytes) on-chip ram (1 kbytes) not used not used h'fb80 h'f77f h'f700 h'efff h'e800 hd64336084 (mask-rom version) h'0000 h'0041 h'0042 h'ff7f h'ff80 h'ffff h'7fff interrupt vector internal i/o register interrupt i/o register on-chip rom (32 kbytes) on-chip ram (2 kbytes) on-chip ram (1 kbytes) not used not used not used figure 2.1 memory map (2) section 2 cpu rev. 2.00 sep. 23, 2005 page 12 of 472 rej09b0160-0200 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition-code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: ccr: i: ui: stack pointer program counter condition-code register interrupt mask bit user bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers (ern) control registers (cr) [legend] (sp) figure 2.2 cpu registers section 2 cpu rev. 2.00 sep. 23, 2005 page 13 of 472 rej09b0160-0200 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address register s and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register . figure 2.3 illustrates the usage of the general registers. when the genera l registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the relationship between the stack pointer and the stack area. section 2 cpu rev. 2.00 sep. 23, 2005 page 14 of 472 rej09b0160-0200 sp (er7) empty area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. op erations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a.1, instruction list. section 2 cpu rev. 2.00 sep. 23, 2005 page 15 of 472 rej09b0160-0200 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an e xception-handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h fl ag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructi ons, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. section 2 cpu rev. 2.00 sep. 23, 2005 page 16 of 472 rej09b0160-0200 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 7 0 7 0 msb lsb msb lsb 70 4 3 don't care don't care don't care 7 0 4 3 70 don't care 65432 71 0 7 0 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general register data formats (1) section 2 cpu rev. 2.00 sep. 23, 2005 page 17 of 472 rej09b0160-0200 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format general register word data word data rn en longword data legend ern figure 2.5 general register data formats (2) section 2 cpu rev. 2.00 sep. 23, 2005 page 18 of 472 rej09b0160-0200 2.3.2 memory data formats figure 2.6 shows the data formats in memory. the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd addr ess, an address error does not occur, however the least significant bit of the ad dress is regarded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 (sp) is used as an address register to access the stack area, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats section 2 cpu rev. 2.00 sep. 23, 2005 page 19 of 472 rej09b0160-0200 2.4 instruction set 2.4.1 table of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length section 2 cpu rev. 2.00 sep. 23, 2005 page 20 of 472 rej09b0160-0200 note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers/address register (er0 to er7). table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is id entical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 2.00 sep. 23, 2005 page 21 of 472 rej09b0160-0200 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on da ta in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte dat a in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 2.00 sep. 23, 2005 page 22 of 472 rej09b0160-0200 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arith metic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 2.00 sep. 23, 2005 page 23 of 472 rej09b0160-0200 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement (logical complement) of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword section 2 cpu rev. 2.00 sep. 23, 2005 page 24 of 472 rej09b0160-0200 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ( section 2 cpu rev. 2.00 sep. 23, 2005 page 25 of 472 rej09b0160-0200 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( section 2 cpu rev. 2.00 sep. 23, 2005 page 26 of 472 rej09b0160-0200 table 2.7 branch instructions instruction size function bcc * branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. rts returns from a subroutine note: * bcc is the general name for conditional branch instructions. section 2 cpu rev. 2.00 sep. 23, 2005 page 27 of 472 rej09b0160-0200 table 2.8 system control instructions instruction size * function trapa ? starts trap-instructi on exception handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr moves the source operand contents to the ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ccr logically ands the ccr with immediate data. orc b ccr #imm ccr logically ors the ccr with immediate data. xorc b ccr #imm ccr logically xors the ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word section 2 cpu rev. 2.00 sep. 23, 2005 page 28 of 472 rej09b0160-0200 table 2.9 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l?1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction be gins as soon as the transfer is completed. section 2 cpu rev. 2.00 sep. 23, 2005 page 29 of 472 rej09b0160-0200 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an eff ective address extension (e a), and a condition field (cc). figure 2.7 shows examples of instruction formats. ? operation field indicates the function of the instruction, the ad dressing mode, and the operation to be carried out on the operand. the operation field always in cludes the first four bits of the instruction. some instructions have two operation fields. ? register field specifies a general register. address registers ar e specified by 3 bits, and data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. ? effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. a24-bit address or displacement is treated as a 32-bit data in wh ich the first 8 bits are 0 (h'00). ? condition field specifies the branching condi tion of bcc instructions. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats section 2 cpu rev. 2.00 sep. 23, 2005 page 30 of 472 rej09b0160-0200 2.5 addressing modes and effective address calculation the following describes the h8/300h cpu. in this lsi, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the regi ster direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displa cement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx: 8/#xx:16/#xx:32 7 program-counter relati ve @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 section 2 cpu rev. 2.00 sep. 23, 2005 page 31 of 472 rej09b0160-0200 (1) register direct ? rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. (2) register indirect ? @ern the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory. (3) register indirect with displacement ? @(d:16, ern) or @(d:24, ern) a 16-bit or 24-bit displacement cont ained in the instruction is adde d to an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacemen t is sign-extended when added. (4) register indirect with po st-increment or pre-decrement ? @ern+ or @-ern ? register indirect with post-increment ? @ern+ the register field of the instruction code specifies an address register (ern) the lower 24 bits of which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longwo rd access. for the word or longword access, the register value should be even. ? register indirect with pre-decrement ? @-ern the value 1, 2, or 4 is subtracted from an addr ess register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result is the addres s of a memory operand. the result is also stored in the address register . the value subtracted is 1 for byte access, 2 for word access, or 4 for l ongword access. for the word or lo ngword access, the register value should be even. (5) absolute address ? @aa:8, @aa:16, @aa:24 the instruction code contains the absolute addr ess of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign ex tension. a 24-bit absolute address can access the entire address space. section 2 cpu rev. 2.00 sep. 23, 2005 page 32 of 472 rej09b0160-0200 the access ranges of absolute addr esses for the group of this lsi are those shown in table 2.11, because the upper 8 bits are ignored. table 2.11 absolute address access ranges absolute address access range 8 bits (@aa:8) h'ff00 to h'ffff 16 bits (@aa:16) h'0000 to h'ffff 24 bits (@aa:24) h'0000 to h'ffff (6) immediate #xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative @(d:8, pc) or @(d:16, pc) this mode is used in the bsr instruction. an 8-bi t or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect @@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memo ry operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byt e of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area. section 2 cpu rev. 2.00 sep. 23, 2005 page 33 of 472 rej09b0160-0200 specified by @aa:8 branch address dummy figure 2.8 branch a ddress specification in memory indirect mode section 2 cpu rev. 2.00 sep. 23, 2005 page 34 of 472 rej09b0160-0200 2.5.2 effective address calculation table 2.12 indicates how effectiv e addresses are calculated in each addressing mode. in this lsi the upper 8 bits of the ef fective address are ignored in order to generate a 16-bit effective address. table 2.12 effective ad dress calculation (1) no 1 r o p 31 0 23 2 3 registe r indirect with dis placement @(d: 16,ern) or @(d: 24,ern) 4 r o p disp r op rm op rn 3 1 0 0 r o p 2 3 0 31 0 dis p 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size. section 2 cpu rev. 2.00 sep. 23, 2005 page 35 of 472 rej09b0160-0200 table 2.12 effective ad dress calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa:24 abs 15 16 23 0 o p abs 6 o p imm #xx:8/#xx:16/#xx:32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 p rogr am- counter re lativ e @ (d:8 ,pc ) @( d:16 ,pc) m em ory indirect @@ aa :8 23 0 di s p 0 23 0 di s p op 23 op 8 abs 23 0 abs h' 0000 7 8 0 1 5 23 0 1 5 h' 00 16 [legend] r, rm,rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address pc contents sign extension memory contents section 2 cpu rev. 2.00 sep. 23, 2005 page 36 of 472 rej09b0160-0200 2.6 basic bus cycle cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). the period from a rising edge of or sub to the next rising edge is called one stat e. a bus cycle consists of two states or three states. the cycle differs depending on whet her access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states . the data bus width is 16 bits, allowing access in byte or word size. figure 2.9 shows the on-chip me mory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub ? or ? figure 2.9 on-chip memory access cycle section 2 cpu rev. 2.00 sep. 23, 2005 page 37 of 472 rej09b0160-0200 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for description on the data bus width and number of accessing states of each register, refer to sect ion 19.1, register addresses (address order). registers with 16-bit data bus width can be accessed by word size only. registers with 8-bit data bus width can be accessed by byte or word size. wh en a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. in two-state access, the operation timing is the same as that for on-chip memory. figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub or figure 2.10 on-chip peripheral mo dule access cycle (3-state access) section 2 cpu rev. 2.00 sep. 23, 2005 page 38 of 472 rej09b0160-0200 2.7 cpu states there are four cpu states: the re set state, program execution st ate, program halt state, and exception-handling state. the program execution state includes active mode and subactive mode. for the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. these states are shown in figure 2.11. figure 2.12 sh ows the state transitions. for details on program execution state and program halt state, refer to section 6, power-down modes. for details on exception processing, refer to section 3, exception handling. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode subactive mode sleep mode subsleep mode power-down modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized standby mode figure 2.11 cpu operation states section 2 cpu rev. 2.00 sep. 23, 2005 page 39 of 472 rej09b0160-0200 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in additio n to the rom, ram, and on-chip i/o registers areas available to the user. when da ta is transferred from cpu to empty areas, the transferred data will be lost. this action may al so cause the cpu to malfunction. when data is transferred from an empty ar ea to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instru ction and transfers th e byte size of data indicated by r4l, which starts from the address indicated by r5, to the address indicated by r6. set r4l and r6 so that the end address of the destination address (value of r6 + r4l) does not exceed h'ffff (the value of r6 must not change from h'ffff to h'0000 during execution). 2.8.3 bit-manipulation instruction the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, an d write data to the same address again in byte units. special care is required wh en using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, becau se this may rewrite data of a bit other than the bit to be manipulated. section 2 cpu rev. 2.00 sep. 23, 2005 page 40 of 472 rej09b0160-0200 (1) bit manipulation for two registers assigned to the same address ? example 1: bit manipulation for the timer load re gister and timer counter (applicable for timer b1 in the h8/36087 group.) figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit-ma nipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two regist ers share the same address, the following operations takes place. a. data is read in byte units. b. the cpu sets or resets the bit to be manipulated with the bit-manipulation instruction. c. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal data bus figure 2.13 example of timer configuration with two registers allocated to same address ? example 2: the bset instruction is executed for port 5. p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high- level signal at p50 with a bset instruction is shown below. section 2 cpu rev. 2.00 sep. 23, 2005 page 41 of 472 rej09b0160-0200 ? prior to executing bset instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bset instruction executed instruction bset #0, @pdr5 the bset instruction is executed for port 5. ? after executing bset instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 0 1 0 0 0 0 0 1 ? description on operation 1. when the bset instruction is exec uted, first the cpu reads port 5. since p57 and p56 are input pins, the cpu re ads the pin states (low-level and high- level input). p55 to p50 are output pins, so the cpu reads the value in pdr5. in this example pdr5 has a value of h'80, but the value read by the cpu is h'40. 2. next, the cpu sets bit 0 of the read data to 1, changing the pdr5 data to h'41. 3. finally, the cpu writes h'41 to pdr5, completing execution of bset instruction. as a result of the bset instruction, bit 0 in pdr5 becomes 1, and p50 outputs a high- level signal. however, bits 7 and 6 of pdr5 end up with different values. to prevent this problem, store a copy of the pdr5 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr5. section 2 cpu rev. 2.00 sep. 23, 2005 page 42 of 472 rej09b0160-0200 ? prior to executing bset instruction mov.b #80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 ? bset instruction executed bset #0, @ram0 the bset instruction is executed designating the pdr5 work area (ram0). ? after executing bset instruction mov.b @ram0, r0l mov.b r0l, @pdr5 the work area (ram0) va lue is written to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1 section 2 cpu rev. 2.00 sep. 23, 2005 page 43 of 472 rej09b0160-0200 (2) bit manipulation in a register containing a write-only bit ? example 3: bclr instruction executed designating port 5 control register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. ? prior to executing bclr instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bclr instruction executed bclr #0, @pcr5 the bclr instruction is executed for pcr5. ? after executing bclr instruction p57 p56 p55 p54 p53 p52 p51 p50 input/output output output output output output ou tput output input pin state low level high level low level low level low level low level low level high level pcr5 1 1 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ? description on operation a. when the bclr instruction is executed, first the cpu r eads pcr5. since pcr5 is a write-only register, the cpu reads a value of h'ff, even though the pcr5 value is actually h'3f. b. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. c. finally, h'fe is written to pcr5 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr5 becomes 0, making p50 an input port. however, bits 7 and 6 in pcr5 change to 1, so that p57 and p56 change from input pins to output pins. to prevent this problem, store a copy of the pdr5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to pdr5. section 2 cpu rev. 2.00 sep. 23, 2005 page 44 of 472 rej09b0160-0200 ? prior to executing bclr instruction mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr5 the pcr5 value (h'3f) is written to a work area in memory (ram0) as well as to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1 ? bclr instruction executed bclr #0, @ram0 the bclr instructions executed for the pcr5 work area (ram0). ? after executing bclr instruction mov.b @ram0, r0l mov.b r0l, @pcr5 the work area (ram0) va lue is written to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output out put output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0 section 3 exception handling rev. 2.00 sep. 23, 2005 page 45 of 472 rej09b0160-0200 section 3 exception handling exception handling may be caused by a reset, a trap instruction (trapa), or interrupts. ? reset a reset has the highest exception priority. exceptio n handling starts as soon as the reset is cleared by the res pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the res pin. ? trap instruction exception handling starts wh en a trap instruction (tra pa) is executed. the trapa instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction co de. exception handling can be ex ecuted at all times in the program execution state, regardless of the setting of the i bit in ccr. ? interrupts external interrupts other than nmi and internal interrupts other than address break are masked by the i bit in ccr, and kept masked while the i bit is set to 1. exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. section 3 exception handling rev. 2.00 sep. 23, 2005 page 46 of 472 rej09b0160-0200 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority. table 3.1 exception sou rces and vector address relative module exception sources vector number vector address priority res pin watchdog timer reset 0 h'0000 to h'0001 high ? reserved for system use 1 to 6 h'0002 to h'000d external interrupt pin nmi 7 h'000e to h'000f cpu trap instruction (#0) 8 h'0010 to h'0011 (#1) 9 h'0012 to h'0013 (#2) 10 h'0014 to h'0015 (#3) 11 h'0016 to h'0017 address break break conditions satisfied 12 h'0018 to h'0019 cpu direct transition by executing the sleep instruction 13 h'001a to h'001b external interrupt pin irq0 14 h'001c to h'001d irq1 15 h'001e to h'001f irq2 16 h'0020 to h'0021 irq3 17 h'0022 to h'0023 wkp 18 h'0024 to h'0025 rtc overflow 19 h'0026 to h'0027 ? reserved for system us e 20 h'0028 to h'0029 timer v timer v compare match a timer v compare match b timer v overflow 22 h'002c to h'002d sci3 sci3 receive data full sci3 transmit data empty sci3 transmit end sci3 receive error 23 h'002e to h'002f low section 3 exception handling rev. 2.00 sep. 23, 2005 page 47 of 472 rej09b0160-0200 relative module exception sources vector number vector address priority iic2 transmit data empty transmit end receive data full arbitration lost/overrun error nack detection stop conditions detected 24 h'0030 to h'0031 high a/d converter a/d conversi on end 25 h'0032 to h'0033 timer z compare match/input capture a0 to d0 timer z overflow 26 h'0034 to h'0035 compare match/input capture a1 to d1 timer z overflow timer z underflow 27 h'0036 to h'0037 timer b1 timer b1 overflow 29 h'003a to h'003b sci3_2 receive data full transmit data empty transmit end receive error 32 h'0040 to h'0041 low 3.2 register descriptions interrupts are controlled by the following registers. ? interrupt edge select register 1 (iegr1) ? interrupt edge select register 2 (iegr2) ? interrupt enable register 1 (ienr1) ? interrupt enable register 2 (ienr2) ? interrupt flag register 1 (irr1) ? interrupt flag register 2 (irr2) ? wakeup interrupt flag register (iwpr) section 3 exception handling rev. 2.00 sep. 23, 2005 page 48 of 472 rej09b0160-0200 3.2.1 interrupt edge se lect register 1 (iegr1) iegr1 selects the direction of an edge that generates interrupt requests of pins nmi and irq3 to irq0 . bit bit name initial value r/w description 7 nmieg 0 r/w nmi edge select 0: falling edge of nmi pin input is detected 1: rising edge of nmi pin input is detected 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 ieg3 0 r/w irq3 edge select 0: falling edge of irq3 pin input is detected 1: rising edge of irq3 pin input is detected 2 ieg2 0 r/w irq2 edge select 0: falling edge of irq2 pin input is detected 1: rising edge of irq2 pin input is detected 1 ieg1 0 r/w irq1 edge select 0: falling edge of irq1 pin input is detected 1: rising edge of irq1 pin input is detected 0 ieg0 0 r/w irq0 edge select 0: falling edge of irq0 pin input is detected 1: rising edge of irq0 pin input is detected section 3 exception handling rev. 2.00 sep. 23, 2005 page 49 of 472 rej09b0160-0200 3.2.2 interrupt edge se lect register 2 (iegr2) iegr2 selects the direction of an edge that generates interrupt requests of the pins adtrg and wkp5 to wkp0 . bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 wpeg5 0 r/w wkp5 edge select 0: falling edge of wkp5 ( adtrg ) pin input is detected 1: rising edge of wkp5 ( adtrg ) pin input is detected 4 wpeg4 0 r/w wkp4 edge select 0: falling edge of wkp4 pin input is detected 1: rising edge of wkp4 pin input is detected 3 wpeg3 0 r/w wkp3 edge select 0: falling edge of wkp3 pin input is detected 1: rising edge of wkp3 pin input is detected 2 wpeg2 0 r/w wkp2 edge select 0: falling edge of wkp2 pin input is detected 1: rising edge of wkp2 pin input is detected 1 wpeg1 0 r/w wkp1edge select 0: falling edge of wkp1 pin input is detected 1: rising edge of wkp1 pin input is detected 0 wpeg0 0 r/w wkp0 edge select 0: falling edge of wkp0 pin input is detected 1: rising edge of wkp0 pin input is detected section 3 exception handling rev. 2.00 sep. 23, 2005 page 50 of 472 rej09b0160-0200 3.2.3 interrupt enable register 1 (ienr1) ienr1 enables direct transition interrupts, rt c interrupts, and external pin interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transfer interrupt enable when this bit is set to 1, direct transition interrupt requests are enabled. 6 ienta 0 r/w rtc interrupt enable when this bit is set to 1, rtc interrupt requests are enabled. 5 ienwp 0 r/w wakeup interrupt enable this bit is an enable bit, which is common to the pins wkp5 to wkp0 . when the bit is set to 1, interrupt requests are enabled. 4 ? 1 ? reserved this bit is always read as 1. 3 ien3 0 r/w irq3 interrupt enable when this bit is set to 1, interrupt requests of the irq3 pin are enabled. 2 ien2 0 r/w irq2 interrupt enable when this bit is set to 1, interrupt requests of the irq2 pin are enabled. 1 ien1 0 r/w irq1 interrupt enable when this bit is set to 1, interrupt requests of the irq1 pin are enabled. 0 ien0 0 r/w irq0 interrupt enable when this bit is set to 1, interrupt requests of the irq0 pin are enabled. when disabling interrupts by clearing bits in an in terrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises between the clear instruction and an interrupt request, exception handling fo r the interrupt will be executed after the clear instruction has been executed. section 3 exception handling rev. 2.00 sep. 23, 2005 page 51 of 472 rej09b0160-0200 3.2.4 interrupt enable register 2 (ienr2) ienr2 enables, timer b1 overflow interrupts. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 ientb1 0 r/w timer b1 interrupt enable when this bit is set to 1, timer b1 overflow interrupt requests are enabled. 4 to 0 ? all 1 ? reserved these bits are always read as 1. when disabling interrupts by clearing bits in an in terrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed. 3.2.5 interrupt flag register 1 (irr1) irr1 is a status flag register for direct transition interrupts, rtc interrupts, and irq3 to irq0 interrupt requests. bit bit name initial value r/w description 7 irrdt 0 r/w direct transfer interrupt request flag [setting condition] when a direct transfer is made by executing a sleep instruction while dton in syscr2 is set to 1. [clearing condition] when irrdt is cleared by writing 0 section 3 exception handling rev. 2.00 sep. 23, 2005 page 52 of 472 rej09b0160-0200 bit bit name initial value r/w description 6 irrta 0 r/w rtc interrupt request flag [setting condition] when the rtc counter value overflows [clearing condition] when irrta is cleared by writing 0 5, 4 ? all 1 ? reserved these bits are always read as 1. 3 irri3 0 r/w irq3 interrupt request flag [setting condition] when irq3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri3 is cleared by writing 0 2 irri2 0 r/w irq2 interrupt request flag [setting condition] when irq2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri2 is cleared by writing 0 1 irri1 0 r/w irq1 interrupt request flag [setting condition] when irq1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri1 is cleared by writing 0 0 irrl0 0 r/w irq0 interrupt request flag [setting condition] when irq0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri0 is cleared by writing 0 section 3 exception handling rev. 2.00 sep. 23, 2005 page 53 of 472 rej09b0160-0200 3.2.6 interrupt flag register 2 (irr2) irr2 is a status flag register for timer b1 overflow interrupts. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 irrtb1 0 r/w timer b1 interrupt request flag [setting condition] when the timer b1 counter value overflows [clearing condition] when irrtb1 is cleared by writing 0 4 to 0 ? all 1 ? reserved these bits are always read as 1. 3.2.7 wakeup interrupt flag register (iwpr) iwpr is a status flag register for wkp5 to wkp0 interrupt requests. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 iwpf5 0 r/w wkp5 interrupt request flag [setting condition] when wkp5 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf5 is cleared by writing 0. 4 iwpf4 0 r/w wkp4 interrupt request flag [setting condition] when wkp4 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf4 is cleared by writing 0. section 3 exception handling rev. 2.00 sep. 23, 2005 page 54 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 iwpf3 0 r/w wkp3 interrupt request flag [setting condition] when wkp3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf3 is cleared by writing 0. 2 iwpf2 0 r/w wkp2 interrupt request flag [setting condition] when wkp2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf2 is cleared by writing 0. 1 iwpf1 0 r/w wkp1 interrupt request flag [setting condition] when wkp1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf1 is cleared by writing 0. 0 iwpf0 0 r/w wkp0 interrupt request flag [setting condition] when wkp0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf0 is cleared by writing 0. section 3 exception handling rev. 2.00 sep. 23, 2005 page 55 of 472 rej09b0160-0200 3.3 reset exception handling when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-up, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after bei ng held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. the reset exception handling sequence is as follows: 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address (from h'0000 to h'0001), the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address. 3.4 interrupt exception handling 3.4.1 external interrupts as the external interrupts, there are nmi, ir q3 to irq0, and wkp5 to wkp0 interrupts. (1) nmi interrupt nmi interrupt is requested by input signal edge to pin nmi . this interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit nmieg in iegr1. nmi is the highest-priority interrupt, and can always be accepted without depending on the i bit value in ccr. (2) irq3 to irq0 interrupts irq3 to irq0 interrupts are requested by input signals to pins irq3 to irq0 . these four interrupts are given different vector addresses, and are detected indi vidually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. when pins irq3 to irq0 are designated for interrupt input in pmr1 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bits ien3 to ien0 in ienr1. section 3 exception handling rev. 2.00 sep. 23, 2005 page 56 of 472 rej09b0160-0200 (3) wkp5 to wkp0 interrupts wkp5 to wkp0 interrupts are requested by input signals to pins wkp 5 to wkp 0. these six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wpeg5 to wpeg0 in iegr2. when pins wkp5 to wkp0 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is se t to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bit ienwp in ienr1. vector fetch internal address bus internal read signal internal write signal internal data bus (16 bits) res internal processing initial program instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) initial program instruction (2) (3) (2) (1) reset cleared figure 3.1 reset sequence section 3 exception handling rev. 2.00 sep. 23, 2005 page 57 of 472 rej09b0160-0200 3.4.2 internal interrupts each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. for rtc interrupt requests and direct transfer interrupt requests generated by execution of a sleep instruction, this function is included in irr1, irr2, ienr1, and ienr2. when an on-chip peripheral module requests an interrupt, the correspon ding interrupt request status flag is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. 1. if an interrupt occurs while the nmi or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. the cpu accepts the nmi and address break wi thout depending on the i bit value. other interrupt requests are accepted, if the i bit is clear ed to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrupt after proces sing of the current instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.2. the pc value pushed onto the stack is the address of the first instruction to be exec uted upon return from interrupt handling. 5. then, the i bit of ccr is set to 1, masking further interrupts excluding the nmi and address break. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector addres s corresponding to th e accepted interrupt, and transfers the address to pc as a start address of the interr upt handling-routine. then a program starts executing from the address indicated in pc. figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. section 3 exception handling rev. 2.00 sep. 23, 2005 page 58 of 472 rej09b0160-0200 pc and ccr saved to stack sp (r7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling [legend] pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr * 3 pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. 3. ignored when returning from the interrupt handling routine. figure 3.2 stack status after exception handling 3.4.4 interrupt response time table 3.2 shows the number of wa it states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 23 15 to 37 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction. section 3 exception handling rev. 2.00 sep. 23, 2005 page 59 of 472 rej09b0160-0200 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ? 2 (6) sp ? 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.3 interrupt sequence section 3 exception handling rev. 2.00 sep. 23, 2005 page 60 of 472 rej09b0160-0200 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx: 16, sp). 3.5.2 notes on stack area use when word data is accessed, the l east significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the st ack pointer (sp: r7) shoul d never indicate an odd address. use push rn (mov.w rn, @?sp) or po p rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to swit ch the functions of external interrupt pins, irq3 to irq0 , and wkp5 to wkp0 , the interrupt request flag may be set to 1. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at l east one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0. interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.4 port mode register setting and interrupt request flag clearing procedure section 4 address break abk0001a_000020020200 rev. 2.00 sep. 23, 2005 page 61 of 472 rej09b0160-0200 section 4 address break the address break simplifies on-board program debugg ing. it requests an address break interrupt when the set break condition is satisfied. the interr upt request is not affected by the i bit of ccr. break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific addr ess. with the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. figure 4.1 shows a block diagram of the address break. barh barl bdrh bdrl abrkcr abrksr internal address bus comparator interrupt generation control circuit internal data bus comparator interrupt [legend] barh, barl: break address register bdrh, bdrl: break data register abrkcr: address break control register abrksr: address break status register figure 4.1 block diagram of address break section 4 address break rev. 2.00 sep. 23, 2005 page 62 of 472 rej09b0160-0200 4.1 register descriptions address break has the following registers. ? address break control register (abrkcr) ? address break status register (abrksr) ? break address regist er (barh, barl) ? break data register (bdrh, bdrl) 4.1.1 address break control register (abrkcr) abrkcr sets address break conditions. bit bit name initial value r/w description 7 rtinte 1 r/w rte interrupt enable when this bit is 0, the interrupt immediately after executing rte is masked a nd then one instruction must be executed. when this bit is 1, the interrupt is not masked. 6 5 csel1 csel0 0 0 r/w r/w condition select 1 and 0 these bits set address break conditions. 00: instruction execution cycle 01: cpu data read cycle 10: cpu data write cycle 11: cpu data read/write cycle 4 3 2 acmp2 acmp1 acmp0 0 0 0 r/w r/w r/w address compare condition select 2 to 0 these bits set the comparison condition between the address set in bar and the internal address bus. 000: compares 16-bit addresses 001: compares upper 12-bit addresses 010: compares upper 8-bit addresses 011: compares upper 4-bit addresses 1xx: reserved (setting prohibited) section 4 address break rev. 2.00 sep. 23, 2005 page 63 of 472 rej09b0160-0200 bit bit name initial value r/w description 1 0 dcmp1 dcmp0 0 0 r/w r/w data compare condition select 1 and 0 these bits set the comparison condition between the data set in bdr and the internal data bus. 00: no data comparison 01: compares lower 8-bit data between bdrl and data bus 10: compares upper 8-bit data between bdrh and data bus 11: compares 16-bit data between bdr and data bus [legend] x: don't care. when an address break is set in the data read cy cle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. table 4.1 shows the access and data bus used. when an i/o register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. for details on da ta widths of each regi ster, see section 19.1, register addresses (address order). table 4.1 access and data bus used word access byte access even address odd address even address odd address rom space upper 8 bits lower 8 bits upper 8 bits upper 8 bits ram space upper 8 bits lower 8 bits upper 8 bits upper 8 bits i/o register with 8-bit data bus width upper 8 bits upper 8 bits upper 8 bits upper 8 bits i/o register with 16-bit data bus width upper 8 bits lower 8 bits ? ? section 4 address break rev. 2.00 sep. 23, 2005 page 64 of 472 rej09b0160-0200 4.1.2 address break status register (abrksr) abrksr consists of the address break interrupt flag and the address break interrupt enable bit. bit bit name initial value r/w description 7 abif 0 r/w address break interrupt flag [setting condition] when the condition set in abrkcr is satisfied [clearing condition] when 0 is written after abif=1 is read 6 abie 0 r/w address break interrupt enable when this bit is 1, an address break interrupt request is enabled. 5 to 0 ? all 1 ? reserved these bits are always read as 1. 4.1.3 break address re gisters (barh, barl) barh and barl are 16-bit read/w rite registers that set the address for generating an address break interrupt. when setting the address break co ndition to the instruction execution cycle, set the first byte address of the instruction. th e initial value of this register is h'ffff. 4.1.4 break data registers (bdrh, bdrl) bdrh and bdrl are 16-bit read/w rite registers that set the data for generating an address break interrupt. bdrh is compared with the upper 8-bit data bus. bdrl is compared with the lower 8- bit data bus. when memory or registers are accessed by byte, the u pper 8-bit data bus is used for even and odd addresses in the data transmission. therefore, comparison data must be set in bdrh for byte access. fo r word access, the data bus used depe nds on the address. see section 4.1.1, address break control register (abrkcr), for details. the initial value of this register is undefined. section 4 address break rev. 2.00 sep. 23, 2005 page 65 of 472 rej09b0160-0200 4.2 operation when the abif and abie bits in abrksr are set to 1, the address break function generates an interrupt request to the cpu. the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and th e conditions set in abrkcr. when the interrupt request is accepted, interr upt exception handling starts after the instruction being executed ends. the address break interrupt is not masked by the i bit in ccr of the cpu. figures 4.2 show the operation examples of the address break interrupt setting. nop instruc- tion prefetch register setting abrkcr = h'80 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 0258 address bus interrupt request 025a 025c 025e sp-2 sp-4 nop instruc- tion prefetch mov instruc- tion 1 prefetch mov instruc- tion 2 prefetch internal processing stack save interrupt acceptance underline indicates the address to be stacked. when the address break is specified in instruction execution cycle figure 4.2 address break in terrupt operation example (1) section 4 address break rev. 2.00 sep. 23, 2005 page 66 of 472 rej09b0160-0200 mov instruc- tion 1 prefetch register setting abrkcr = h'a0 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 025c address bus interrupt request 025e 0260 025a 0262 0264 sp-2 mov instruc- tion 2 prefetch nop instruc- tion prefetch mov instruc- tion execution next instru- ction prefetch internal processing stack save nop instruc- tion prefetch interrupt acceptance underline indicates the address to be stacked. when the address break is specified in the data read cycle figure 4.2 address break in terrupt operation example (2) section 5 clock pulse generators cpg0200a_000020020200 rev. 2.00 sep. 23, 2005 page 67 of 472 rej09b0160-0200 section 5 clock pulse generators clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock puls e generator. the system clock pulse generator consists of a system clock oscillator, a duty co rrection circuit, and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. figure 5.1 shows a block diagram of the clock pulse generators. system clock oscillator subclock oscillator subclock divider duty correction circuit system clock divider prescaler s (13 bits) prescaler w (5 bits) osc 1 osc 2 x 1 x 2 system clock pulse generator osc (f osc ) osc (f osc ) w (f w ) w /2 w /4 sub /2 to /8192 w /8 osc /8 osc osc /16 osc /32 osc /64 w /8 to w /128 subclock pulse generator figure 5.1 block diagram of clock pulse generators the basic clock signals that drive the cpu and on-chip peripheral modules are and sub . the system clock is divided by prescaler s to become a clock signal from /8192 to /2, and the subclock is divided by prescaler w to become a clock signal from w/128 to w/8. both the system clock and subclock signals are prov ided to the on-chip peripheral modules. section 5 clock pulse generators rev. 2.00 sep. 23, 2005 page 68 of 472 rej09b0160-0200 5.1 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. figure 5.2 shows a block diagram of the system clock generator. lpm lpm: low-power mode (standby mode, subactive mode, subsleep mode) 2 1 osc osc figure 5.2 block diagram of system clock generator 5.1.1 connecting crystal resonator figure 5.3 shows a typical method of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. figure 5.4 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 5.1 should be used. 1 2 c 1 c 2 osc osc c = c = 12 pf 20% 12 figure 5.3 typical connect ion to crystal resonator c s c 0 r s osc 1 osc 2 l s figure 5.4 equivalent circuit of crystal resonator section 5 clock pulse generators rev. 2.00 sep. 23, 2005 page 69 of 472 rej09b0160-0200 table 5.1 crystal resonator parameters frequency (mhz) 4 8 10 16 18 r s (max) 120 ? 80 ? 60 ? 50 ? 50 ? c 0 (max) 7 pf 7 pf 7 pf 7 pf 7 pf 5.1.2 connecting ceramic resonator figure 5.5 shows a typical method of connecting a ceramic resonator. osc 1 osc 2 c 1 c 2 c 1 = 30 pf 10% c 2 = 30 pf 10% figure 5.5 typical connect ion to cerami c resonator 5.1.3 external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 5.6 shows a typical connection. the duty cycle of the external clock sign al must be 45 to 55%. osc 1 external clock input osc 2 open figure 5.6 example of external clock input section 5 clock pulse generators rev. 2.00 sep. 23, 2005 page 70 of 472 rej09b0160-0200 5.2 subclock generator figure 5.7 shows a block diagram of the subclock generator. note : registance is a reference value. 2 1 x 8m ? x figure 5.7 block diagram of subclock generator 5.2.1 connecting 32.768-khz crystal resonator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal resonator, as shown in figure 5.8. figure 5.9 shows the equivalent circuit of the 32.768-khz crystal resonator. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 figure 5.8 typical connection to 32.768-khz crystal resonator x 1 x 2 l s c s c o c o = 1.5 pf (typ.) r s = 14 k ? (typ.) f w = 32.768 khz r s note: constants are reference values. figure 5.9 equivalent circuit of 32.768-khz crystal resonator section 5 clock pulse generators rev. 2.00 sep. 23, 2005 page 71 of 472 rej09b0160-0200 5.2.2 pin connection when not using subclock when the subclock is not used, connect pin x 1 to v ss and leave pin x 2 open, as shown in figure 5.10. x 1 v ss x 2 open figure 5.10 pin connection when not using subclock 5.3 prescalers 5.3.1 prescaler s prescaler s is a 13-bit counter using the system cloc k (?) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mo de, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is ini tialized to h'0000. the cp u cannot read or write prescaler s. the output from pres caler s is shared by the on-chi p peripheral modules. the divider ratio can be set separately for each on-chip peri pheral function. in activ e mode and sleep mode, the clock input to prescaler s is determined by the division factor designated by ma2 to ma0 in syscr2. 5.3.2 prescaler w prescaler w is a 5-bit counter using a 32.768 khz signal divided by 4 (? w /4) as its input clock. the divided output is used for clock time base operation of timer a. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the re set state. even in stan dby mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x 1 and x 2 . section 5 clock pulse generators rev. 2.00 sep. 23, 2005 page 72 of 472 rej09b0160-0200 5.4 usage notes 5.4.1 note on resonators resonator characteristics are closely related to boar d design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit constants will differ depending on the resonator element, stray capaci tance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator element manufacturer. design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.4.2 notes on board design when using a crystal resonator (ceramic resonator) , place the resonator and it s load capacitors as close as possible to the osc 1 and osc 2 pins. other signal lines should be routed away from the resonator circuit to prevent induction from interfe ring with correct oscill ation (see figure 5.11). osc 1 osc 2 c 1 c 2 signal a signal b avoid figure 5.11 example of incorrect board design section 6 power-down modes lpw3002a_000120030300 rev. 2.00 sep. 23, 2005 page 73 of 472 rej09b0160-0200 section 6 power-down modes this lsi has six modes of operation after a reset. these include a normal active mode and four power-down modes, in which power consumption is significantly reduced. module standby mode reduces power consumption by selectively halting on-chip module functions. ? active mode the cpu and all on-chip peripheral modules are operable on the system clock. the system clock frequency can be selected from osc, osc/8, osc/16, osc/32, and osc/64. ? subactive mode the cpu and all on-chip peripheral modules are operable on the subclock. the subclock frequency can be selected from w/2, w/4, and w/8. ? sleep mode the cpu halts. on-chip peripheral module s are operable on the system clock. ? subsleep mode the cpu halts. on-chip peripheral modules are operable on the subclock. ? standby mode the cpu and all on-chip peripheral modules halt. when the clock time-base function is selected, the rtc is operable. ? module standby mode independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 74 of 472 rej09b0160-0200 6.1 register descriptions the registers related to power-down modes are listed below. ? system control register 1 (syscr1) ? system control register 2 (syscr2) ? module standby control register 1 (mstcr1) ? module standby control register 2 (mstcr2) 6.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit selects the mode to tr ansit after the execution of the sleep instruction. 0: enters sleep mode or subsleep mode. 1: enters standby mode. for details, see table 6.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or subsleep mode to active mode or sleep mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. the relationship between the specified value and the number of wait states is shown in table 6.1. when an external clock is to be used, the minimum value (sts2 = sts1 = sts0 =1) is recommended. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 75 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 nesel 0 r/w noise eliminat ion sampling frequency select the subclock pulse generator generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 18 mhz, clear nesel to 0. 0: sampling rate is osc /16 1: sampling rate is osc /4 2 to 0 ? all 0 ? reserved these bits are always read as 0. table 6.1 operating frequency and waiting time bit name operating frequency sts2 sts1 sts0 waiting time 18 mhz 16 mhz 10 mhz 8 mhz 4 mhz 0 0 0 8,192 states 0.4 0.5 0.8 1.0 2.0 1 16,384 states 0.9 1.0 1.6 2.0 4.1 1 0 32,768 states 1.8 2.0 3.3 4.1 8.2 1 65,536 states 3.6 4.1 6.6 8.2 16.4 1 0 0 131,072 states 7.2 8.2 13.1 16.4 32.8 1 1,024 states 0.05 0.06 0.10 0.13 0.26 1 0 128 states 0.00 0.00 0.01 0.02 0.03 1 16 states 0.00 0.00 0.00 0.00 0.00 note: time unit is ms. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 76 of 472 rej09b0160-0200 6.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 6 5 smsel lson dton 0 0 0 r/w r/w r/w sleep mode selection low speed on flag direct transfer on flag these bits select the mode to enter after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 4 3 2 ma2 ma1 ma0 0 0 0 r/w r/w r/w active mode clock select 2 to 0 these bits select the operating clock frequency in active and sleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 0xx: osc 100: osc /8 101: osc /16 110: osc /32 111: osc /64 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 these bits select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 00: w /8 01: w /4 1x: w /2 [legend] x: don't care. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 77 of 472 rej09b0160-0200 6.1.3 module standby control register 1 (mstcr1) mstcr1 allows the on-chip peripheral module s to enter a standby state in module units. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 mstiic 0 r/w iic2 module standby iic2 enters standby mode when this bit is set to 1 5 msts3 0 r/w sci3 module standby sci3 enters standby mode when this bit is set to 1 4 mstad 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is set to 1 3 mstwd 0 r/w watchdog timer module standby watchdog timer enters standby mode when this bit is set to 1.when the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 ? 0 ? reserved this bit is always read as 0. 1 msttv 0 r/w timer v module standby timer v enters standby mode when this bit is set to 1 0 mstta 0 r/w rtc module standby rtc enters standby mode when this bit is set to 1 section 6 power-down modes rev. 2.00 sep. 23, 2005 page 78 of 472 rej09b0160-0200 6.1.4 module standby control register 2 (mstcr2) mstcr2 allows the on-chip peripheral modules to enter a standby state in module units. bit bit name initial value r/w description 7 msts3_2 0 r/w sci3_2 module standby sci3_2 enters standby mode when this bit is set to1 6, 5 ? all 0 ? reserved these bits are always read as 0. 4 msttb1 0 r/w timer b1 module standby timer b1 enters standby mode when this bit is set to1 3, 2 ? all 0 ? reserved these bits are always read as 0. 1 msttz 0 r/w timer z module standby timer z enters standby mode when this bit is set to1 0 mstpwm 0 r/w pwm module standby pwm enters standby mode when this bit is set to1 section 6 power-down modes rev. 2.00 sep. 23, 2005 page 79 of 472 rej09b0160-0200 6.2 mode transitions and states of lsi figure 6.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution stat e. a direct transition between active mode and subactive mode, which ar e both program execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 6.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 6.3 shows the in ternal states of the lsi in each mode. reset state standby mode active mode sleep mode subsleep mode subactive mode program halt state program execution state program halt state sleep instruction sleep instruction interrupt direct transition interrupt direct transition interrupt notes: 1. to make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. details on the mode transition conditions are given in table 6.2. sleep instruction direct transition interrupt direct transition interrupt interrupt sleep instruction interrupt interrupt sleep instruction interrupt sleep instruction figure 6.1 mode transition diagram section 6 power-down modes rev. 2.00 sep. 23, 2005 page 80 of 472 rej09b0160-0200 table 6.2 transition mode after sleep inst ruction execution and transition mode due to interrupt dton ssby smsel lson transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 0 sleep mode active mode 1 subactive mode 1 0 subsleep mode active mode 1 subactive mode 1 x x standby mode active mode 1 x 0 * 0 active mode (direct transition) ? x x 1 subactive mode (direct transition) ? [legend] x: don?t care. note: * when a state transition is performed while sm sel is 1, timer v, sci3, sci3_2 and the a/d converter are reset, and all registers are set to their initial values. to use these functions after entering active mode, reset the registers. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 81 of 472 rej09b0160-0200 table 6.3 internal state in each operating mode function active mode sleep mode subactive mode subsleep mode standby mode system clock oscillator functioning functioning halted halted halted subclock oscillator functioning functi oning functioning functioning functioning instructions functioning halted functioning halted halted cpu operations registers functioning retained functioning retained retained ram functioning retained f unctioning retained retained io ports functioning retained func tioning retained register contents are retained, but output is the high- impedance state. irq3 to irq0 functioning functioni ng functioning functioning functioning external interrupts wkp5 to wkp0 functioning functioning functi oning functioning functioning rtc functioning functioning functioning if the timek eeping time-base function is selected, and retained if not selected peripheral functions timer v functioning functioning reset reset reset watchdog timer functioning functioning retained (functioning if the internal oscillator is selected as a count clock * ) sci3, sci3_2 functioning functioning reset reset reset iic2 functioning functioning retained * retained retained timer b1 functioning functioning retained * retained retained timer z functioning functi oning retained (the counter increments according to subclocks if the internal clock ( ) is selected as a count clock * ) a/d converter functioning functioning reset reset reset note: * registers can be read or written in subactive mode. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 82 of 472 rej09b0160-0200 6.2.1 sleep mode in sleep mode, cpu operation is halted but the on-chip peripheral modules function at the clock frequency set by the ma2, ma1, and ma0 bits in syscr2. cpu register contents are retained. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit of the co ndition code register (ccr) is set to 1 or the requested interrupt is disabled in the interrupt enable register. after sleep mode is cleared, a transition is made to active mode when the lson b it in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 6.2.2 standby mode in standby mode, the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. however, as long as the rated voltage is supplied, the contents of cpu registers, on- chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an in terrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, and interrupt exception handling starts. standby mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire ch ip as soon as the system clock puls e generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.2.3 subsleep mode in subsleep mode, operation of the cpu and on-chip peripheral modules other than rtc is halted. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an in terrupt. when an interrupt is requ ested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. after subsleep mode is section 6 power-down modes rev. 2.00 sep. 23, 2005 page 83 of 472 rej09b0160-0200 cleared, a transition is made to active mode when th e lson bit in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a transition is made to active mode. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire ch ip as soon as the system clock puls e generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.2.4 subactive mode the operating frequency of subactive mode is selected from w /2, w /4, and w /8 by the sa1 and sa0 bits in syscr2. after the sleep instruction is executed, the operatin g frequency changes to the frequency which is set before the execution. when the sleep instruction is executed in subactive mode, a transition to sleep mode, su bsleep mode, standby mode, active mode, or subactive mode is made, depending on the combination of syscr1 and syscr2. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse genera tor starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.3 operating frequency in active mode operation in active mode is clocked at the frequency designated by the ma2, ma1, and ma0 bits in syscr2. the operating frequency changes to the set frequency after sleep instruction execution. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 84 of 472 rej09b0160-0200 6.4 direct transition the cpu can execute programs in two modes: activ e and subactive modes. a direct transition is a transition between these two modes without stoppi ng program execution. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modi fication in active or subactive mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in in terrupt enable register 1, a transition is made instead to sleep or subsleep mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 direct transition from ac tive mode to subactive mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt exception handling states) (tsubcyc after transition) (1) ? example direct transition time = (2 + 1) tosc + 14 8tw = 3tosc + 112tw (when the cpu operating clock of osc w /8 is selected) [legend] tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock () cycle time tsubcyc: subclock (sub) cycle time section 6 power-down modes rev. 2.00 sep. 23, 2005 page 85 of 472 rej09b0160-0200 6.4.2 direct transition from su bactive mode to active mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} (tsubcyc before transition) + {(waiting time set in bits sts2 to sts0) + (number of interrupt exception handling states)} (tcyc after transition) (2) ? example direct transition time = (2 + 1) 8tw + (8192 + 14) tosc = 24tw + 8206tosc (when the cpu operating clock of w /8 osc and a waiting time of 8192 states are selected) [legend] tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 6.5 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the po wer-down mode. module standby mode enables each on-chip peripheral module to enter the standby st ate by setting a bit that corresponds to each module to 1 and cancels the mode by clearing the bit to 0. section 6 power-down modes rev. 2.00 sep. 23, 2005 page 86 of 472 rej09b0160-0200 section 7 rom rom3560a_000120030300 rev. 2.00 sep. 23, 2005 page 87 of 472 rej09b0160-0200 section 7 rom the features of the 56-kbyte flash memories bu ilt into the flash memory (f-ztat) version are summarized below. ? programming/erase methods the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 1 kbyte 4 blocks, 28 kbytes 1 block, 16 kbytes 1 block, and 8 kbytes 1 block for h8/36087f. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability the flash memory can be reprogrammed up to 1,000 times. ? on-board programming on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection sets software protection against fl ash memory programming/erasing. ? power-down mode operation of the power supply circuit can be partly halted in subactive mode. as a result, flash memory can be read with low power consumption. 7.1 block configuration figure 7.1 shows the block configuration of flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the 56-kbyte flash memory is divided into 1 kbyte 4 blocks, 28 kbytes 1 block, 16 kbytes 1 block, and 8 kbytes 1 block. erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. section 7 rom rev. 2.00 sep. 23, 2005 page 88 of 472 rej09b0160-0200 h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0481 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'7fff h'7f80 h'7f81 h'7f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 28 kbytes erase unit h'807f h'8000 h'8001 h'8002 h'80ff h'8080 h'8081 h'8082 h'bfff h'bf80 h'bf81 h'bf82 programming unit: 128 bytes 16 kbytes erase unit h'c07f h'c000 h'c001 h'c002 h'c0ff h'c080 h'c081 h'c082 h'dfff hdf80 h'df81 h'df82 programming unit: 128 bytes 8 kbytes erase unit figure 7.1 flash memory block configuration section 7 rom rev. 2.00 sep. 23, 2005 page 89 of 472 rej09b0160-0200 7.2 register descriptions the flash memory has th e following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? flash memory power control register (flpwcr) ? flash memory enable register (fenr) 7.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for detail s on register setting, refer to section 7.4, flash memory programming/erasing. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to 1 in flmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1. 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. section 7 rom rev. 2.00 sep. 23, 2005 page 90 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program- verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1 while swe=1 and esu=1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1 while swe=1 and psu=1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. 7.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displa ys the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see section 7.5.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0. section 7 rom rev. 2.00 sep. 23, 2005 page 91 of 472 rej09b0160-0200 7.2.3 erase block register 1 (ebr1) ebr1 specifies the flash memory er ase area block. ebr1 is initial ized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 eb6 0 r/w when this bit is set to 1, 8 bytes of h'c000 to h'dfff will be erased. 5 eb5 0 r/w when this bit is set to 1, 16 bytes of h'8000 to h'bfff will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased. section 7 rom rev. 2.00 sep. 23, 2005 page 92 of 472 rej09b0160-0200 7.2.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to th e flash memory power-down mode when the lsi switches to subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operat ion of the power supply circuit of flash memory is retain ed and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory ent ers the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 7.2.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memo ry control registers, flmcr1, flmcr2, ebr1, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 ? all 0 ? reserved these bits are always read as 0. section 7 rom rev. 2.00 sep. 23, 2005 page 93 of 472 rej09b0160-0200 7.3 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, nmi pin settings, and input level of each port, as shown in table 7.1. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entir e flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 7.1 setting programming modes test nmi p85 pb0 pb1 pb2 lsi state after reset end 0 1 x x x x user mode 0 0 1 x x x boot mode 1 x x 0 0 0 programmer mode [legend] x: don?t care. section 7 rom rev. 2.00 sep. 23, 2005 page 94 of 472 rej09b0160-0200 7.3.1 boot mode table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 7.4, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit on e h'55 byte to the chip. if reception could not be performed normally, initia te boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to oper ate the sci properly, set the host's transfer bit rate and system clock frequency of this ls i within the ranges listed in table 7.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control pr ogram, the chip terminat es transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of program data or verify data with the host. the txd pin is high (pcr22 = 1, p22 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointe r (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the nmi pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode. section 7 rom rev. 2.00 sep. 23, 2005 page 95 of 472 rej09b0160-0200 table 7.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. h'55 reception. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase section 7 rom rev. 2.00 sep. 23, 2005 page 96 of 472 rej09b0160-0200 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system cloc k frequency range of lsi 19,200 bps 16 to 18 mhz 9,600 bps 8 to 16 mhz 4,800 bps 4 to 16 mhz 2,400 bps 4 to 16 mhz 7.3.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 7.2 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 7.4, flash memory programming/erasing. section 7 rom rev. 2.00 sep. 23, 2005 page 97 of 472 rej09b0160-0200 ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 7.2 programming/erasing flowchart example in user program mode section 7 rom rev. 2.00 sep. 23, 2005 page 98 of 472 rej09b0160-0200 7.4 flash memory programming/erasing a software method using the cpu is employed to program and erase fl ash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4. 1, program/program-veri fy and sect ion 7.4.2, erase/erase-verify, respectively. 7.4.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data ar ea to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start addr ess in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 7.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1- byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed. section 7 rom rev. 2.00 sep. 23, 2005 page 99 of 472 rej09b0160-0200 8. the maximum number of repetitions of the pr ogram/program-verify sequence of the same bit is 1,000. start end of programming note: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 s apply write pulse * end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 s clear psu bit in flmcr1 wait 5 s n= 1 m= 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data verify data = write data? reprogram data computation additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 m= 0 ? increment address programming failure no clear swe bit in flmcr1 wait 100 s no yes n 6? no yes n 6 ? wait 100 s n 1000 ? n n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory * figure 7.3 program/program-verify flowchart section 7 rom rev. 2.00 sep. 23, 2005 page 100 of 472 rej09b0160-0200 table 7.4 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 1 0 1 ? 1 1 1 remains in erased state table 7.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 7.6 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 ? note: time shown in s. section 7 rom rev. 2.00 sep. 23, 2005 page 101 of 472 rej09b0160-0200 7.4.2 erase/erase-verify when erasing flash memory, the erase/erase-veri fy flowchart shown in figure 7.4 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent ov ererasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in lo ngwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum numb er of repetitions of the erase/erase-verify sequence is 100. 7.4.3 interrupt handli ng when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. section 7 rom rev. 2.00 sep. 23, 2005 page 102 of 472 rej09b0160-0200 erase start set ebr1 enable wdt wait 1 s wait 100 s swe bit 1 n 1 esu bit 1 e bit 1 wait 10 ms e bit 0 wait 10 s esu bit 0 10 s disable wdt read verify data increment address verify data + all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 s wait 2 s ev bit 1 wait 100 s end of erasing note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. swe bit 0 wait 4 s ev bit 0 n 100 ? wait 100 s erase failure swe bit 0 wait 4 s ev bit 0 n n + 1 ye s no ye s ye s ye s ye s no no no * figure 7.4 erase/erase-verify flowchart section 7 rom rev. 2.00 sep. 23, 2005 page 103 of 472 rej09b0160-0200 7.5 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) ar e initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stab ilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristic s section. 7.5.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to prog ram mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. 7.5.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the prog ram/erase operation is forcibly ab orted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are de tected during programming/eras ing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling excluding a reset during programming/erasing ? when a sleep instruction is executed during programming/erasing section 7 rom rev. 2.00 sep. 23, 2005 page 104 of 472 rej09b0160-0200 the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurr ed. program mode or erase mode cannot be re- entered by re-setting the p or e bit. however, pv and ev bit settings are retained, and a transition can be made to verify mode. error protection can be cleared only by a reset. 7.6 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memo ry. use a prom programmer that supports the mcu device type with the on-chip 64-kbyte flash memory (fztat64v3). 7.7 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to at high speed. ? power-down operating mode the power supply circuit of flash memory can be partly halted. as a re sult, flash memory can be read with low power consumption. ? standby mode all flash memory circuits are halted. table 7.7 shows the correspondence between the operating modes of this lsi and the flash memory. in subactive mode, the fl ash memory can be set to operate in power-down mode with the pdwnd bit in flpwcr. when the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in syscr1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. section 7 rom rev. 2.00 sep. 23, 2005 page 105 of 472 rej09b0160-0200 table 7.7 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode section 7 rom rev. 2.00 sep. 23, 2005 page 106 of 472 rej09b0160-0200 section 8 ram ram0500a_000120030300 rev. 2.00 sep. 23, 2005 page 107 of 472 rej09b0160-0200 section 8 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address flash memory version (f-ztat tm version) h8/36087f 4 kbytes h'e800 to h'efff, h'f780 to h'ff7f * h8/36087 3 kbytes h'e800 to h'efff, h'fb80 to h'ff7f h8/36086 3 kbytes h'e800 to h'efff, h'fb80 to h'ff7f h8/36085 3 kbytes h'e800 to h'efff, h'fb80 to h'ff7f h8/36084 3 kbytes h'e800 to h'efff, h'fb80 to h'ff7f h8/36083 3 kbytes h'e800 to h'efff, h'fb80 to h'ff7f mask-rom version h8/36082 3 kbytes h'e800 to h'efff, h'fb80 to h'ff7f note: * when the e7 or e8 is used, area h 'f780 to h'fb7f must not be accessed. section 8 ram rev. 2.00 sep. 23, 2005 page 108 of 472 rej09b0160-0200 section 9 i/o ports rev. 2.00 sep. 23, 2005 page 109 of 472 rej09b0160-0200 section 9 i/o ports the group of this lsi has forty-five general i/o ports and eight general input-only ports. port 6 is a large current port, which can drive 10 ma (@v ol = 1.0 v) when a low level signal is output. any of these ports can become an input port immedi ately after a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. th e registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on-chip peripheral module. general i/o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for functions in each port, see appendix b.1, i/o port block diagrams. for the execution of bit- manipulation instructions to the port control register and port data register, see section 2.8.3, bit manipulation instruction. 9.1 port 1 port 1 is a general i/o port also functioning as irq interrupt input pins, an rtc output pin, a 14- bit pwm output pin, a timer b1 input pin, and a timer v input pin. figure 9.1 shows its pin configuration. p17/ irq3 /trgv p16/ irq2 p15/ irq1 /tmib1 p14/ irq0 p12 p11/pwm p10/tmow port 1 figure 9.1 port 1 pin configuration port 1 has the following registers. ? port mode register 1 (pmr1) ? port control register 1 (pcr1) ? port data register 1 (pdr1) ? port pull-up control register 1 (pucr1) section 9 i/o ports rev. 2.00 sep. 23, 2005 page 110 of 472 rej09b0160-0200 9.1.1 port mode register 1 (pmr1) pmr1 switches the functions of pins in port 1 and port 2. bit bit name initial value r/w description 7 irq3 0 r/w this bit selects the function of pin p17/ irq3 /trgv. 0: general i/o port 1: irq3 /trgv input pin 6 irq2 0 r/w this bit selects the function of pin p16/ irq2 . 0: general i/o port 1: irq2 input pin 5 irq1 0 r/w this bit selects the function of pin p15/ irq1 /tmib1. 0: general i/o port 1: irq1 /tmib1 input pin 4 irq0 0 r/w this bit selects the function of pin p14/ irq0 . 0: general i/o port 1: irq0 input pin 3 txd2 0 r/w this bit selects the function of pin p72/txd_2. 0: general i/o port 1: txd_2 output pin 2 pwm 0 r/w this bit selects the function of pin p11/pwm. 0: general i/o port 1: pwm output pin 1 txd 0 r/w this bit selects the function of pin p22/txd. 0: general i/o port 1: txd output pin 0 tmow 0 r/w this bit selects the function of pin p10/tmow. 0: general i/o port 1: tmow output pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 111 of 472 rej09b0160-0200 9.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 0 0 0 0 ? 0 0 0 w w w w ? w w w when the corresponding pin is designated in pmr1 as a general i/o pin, setting a pcr1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit. 9.1.3 port data register 1 (pdr1) pdr1 is a general i/o port data register of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 ? p12 p11 p10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr1 stores output data for port 1 pins. if pdr1 is read while pcr1 bi ts are set to 1, the value stored in pdr1 are read. if pdr1 is read while pcr1 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr1. bit 3 is a reserved bit. this bit is always read as 1. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 112 of 472 rej09b0160-0200 9.1.4 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w only bits for which pcr1 is cleared are valid. the pull-up mos of p17 to p14 and p12 to p10 pins enter the on- state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. bit 3 is a reserved bit. this bit is always read as 1. 9.1.5 pin functions the correspondence between the register specification and the port functions is shown below. ? p17/irq3/trgv pin register pmr1 pcr1 bit name irq3 pcr17 pin function setting value 0 0 p17 input pin 1 p17 output pin 1 x irq3 input/trgv input pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 113 of 472 rej09b0160-0200 ? p16/ irq2 pin register pmr1 pcr1 bit name irq2 pcr16 pin function setting value 0 0 p16 input pin 1 p16 output pin 1 x irq2 input pin [legend] x: don't care. ? p15/ irq1 /tmib1 pin register pmr1 pcr1 bit name irq1 pcr15 pin function setting value 0 0 p15 input pin 1 p15 output pin 1 x irq1 input/tmib1 input pin [legend] x: don't care. ? p14/ irq0 pin register pmr1 pcr1 bit name irq0 pcr14 pin function setting value 0 0 p14 input pin 1 p14 output pin 1 x irq0 input pin [legend] x: don't care. ? p12 pin register pcr1 bit name pcr12 pin function 0 p12 input pin setting value 1 p12 output pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 114 of 472 rej09b0160-0200 ? p11/pwm pin register pmr1 pcr1 bit name pwm pcr11 pin function setting value 0 0 p11 input pin 1 p11 output pin 1 x pwm output pin [legend] x: don't care. ? p10/tmow pin register pmr1 pcr1 bit name tmow pcr10 pin function setting value 0 0 p10 input pin 1 p10 output pin 1 x tmow output pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 115 of 472 rej09b0160-0200 9.2 port 2 port 2 is a general i/o port also functioning as sci3 i/o pins. each pin of the port 2 is shown in figure 9.2. the register settings of pmr1and sci3 have priority for functions of the pins for both uses. p24 p23 p22/txd p21/rxd p20/sck3 port 2 figure 9.2 port 2 pin configuration port 2 has the following registers. ? port control register 2 (pcr2) ? port data register 2 (pdr2) ? port mode register 3 (pmr3) 9.2.1 port control register 2 (pcr2) pcr2 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 2. bit bit name initial value r/w description 7 to 5 ? ? ? reserved 4 3 2 1 0 pcr24 pcr23 pcr22 pcr21 pcr20 0 0 0 0 0 w w w w w when each of the port 2 pins p24 to p20 functions as a general i/o port, setting a pcr2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 116 of 472 rej09b0160-0200 9.2.2 port data register 2 (pdr2) pdr2 is a general i/o port data register of port 2. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 2 1 0 p24 p23 p22 p21 p20 0 0 0 0 0 r/w r/w r/w r/w r/w pdr2 stores output data for port 2 pins. if pdr2 is read while pcr2 bi ts are set to 1, the value stored in pdr2 is read. if pdr2 is read while pcr2 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr2. 9.2.3 port mode register 3 (pmr3) pmr3 selects the cmos output or nmos open-drain output for port 2. bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0. 4 3 pof24 pof23 0 0 r/w r/w when the bit is set to 1, the corresponding pin is cut off by pmos and it functions as the nmos open-drain output. when cleared to 0, the pin functions as the cmos output. 2 to 0 ? all 1 ? reserved these bits are always read as 1. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 117 of 472 rej09b0160-0200 9.2.4 pin functions the correspondence between the register specification and the port functions is shown below. ? p24 pin register pcr2 bit name pcr24 pin function setting value 0 p24 input pin 1 p24 output pin ? p23 pin register pcr2 bit name pcr23 pin function setting value 0 p23 input pin 1 p23 output pin ? p22/txd pin register pmr1 pcr2 bit name txd pcr22 pin function setting value 0 0 p22 input pin 1 p22 output pin 1 x txd output pin [legend] x: don't care. ? p21/rxd pin register scr3 pcr2 bit name re pcr21 pin function setting value 0 0 p21 input pin 1 p21 output pin 1 x rxd input pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 118 of 472 rej09b0160-0200 ? p20/sck3 pin register scr3 smr pcr2 bit name cke1 cke0 com pcr20 pin function setting value 0 0 0 0 p20 input pin 1 p20 output pin 0 0 1 x sck3 output pin 0 1 x x sck3 output pin 1 x x x sck3 input pin [legend] x: don't care. 9.3 port 3 port 3 is a general i/o port. each pin of the port 3 is shown in figure 9.3. p37 p36 p35 p34 p33 p32 p31 p30 port 3 figure 9.3 port 3 pin configuration port 3 has the following registers. ? port control register 3 (pcr3) ? port data register 3 (pdr3) section 9 i/o ports rev. 2.00 sep. 23, 2005 page 119 of 472 rej09b0160-0200 9.3.1 port control register 3 (pcr3) pcr3 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 0 0 0 0 0 0 0 0 w w w w w w w w setting a pcr3 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.3.2 port data register 3 (pdr3) pdr3 is a general i/o port data register of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p37 p36 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr3 stores output data for port 3 pins. if pdr3 is read while pcr3 bi ts are set to 1, the value stored in pdr3 is read. if pdr3 is read while pcr3 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr3. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 120 of 472 rej09b0160-0200 9.3.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p37 pin register pcr3 bit name pcr37 pin function setting value 0 p37 input pin 1 p37 output pin ? p36 pin register pcr3 bit name pcr36 pin function setting value 0 p36 input pin 1 p36 output pin ? p35 pin register pcr3 bit name pcr35 pin function setting value 0 p35 input pin 1 p35 output pin ? p34 pin register pcr3 bit name pcr34 pin function setting value 0 p34 input pin 1 p34 output pin ? p33 pin register pcr3 bit name pcr33 pin function setting value 0 p33 input pin 1 p33 output pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 121 of 472 rej09b0160-0200 ? p32 pin register pcr3 bit name pcr32 pin function setting value 0 p32 input pin 1 p32 output pin ? p31 pin register pcr3 bit name pcr31 pin function setting value 0 p31 input pin 1 p31 output pin ? p30 pin register pcr3 bit name pcr30 pin function setting value 0 p30 input pin 1 p30 output pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 122 of 472 rej09b0160-0200 9.4 port 5 port 5 is a general i/o port also functioning as an i 2 c bus interface i/o pin, an a/d trigger input pin, and wakeup interrupt input pin. each pin of the port 5 is shown in figure 9.4. the register setting of the i 2 c bus interface register has priority for functions of the pins p57/scl and p56/sda. since the output buffer for pins p56 and p57 has the nmos push-pull structure, it differs from an output buffer with the cmos stru cture in the high-level output characteristics (see section 20, electrical characteristics). p57/scl p56/sda p55/ wkp5 / adtrg p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 port 5 figure 9.4 port 5 pin configuration port 5 has the following registers. ? port mode register 5 (pmr5) ? port control register 5 (pcr5) ? port data register 5 (pdr5) ? port pull-up control register 5 (pucr5) section 9 i/o ports rev. 2.00 sep. 23, 2005 page 123 of 472 rej09b0160-0200 9.4.1 port mode register 5 (pmr5) pmr5 switches the functions of pins in port 5. bit bit name initial value r/w description 7 6 pof57 pof56 0 0 r/w r/w when the bit is set to 1, the corresponding pin is cut off by pmos and it functions as the nmos open-drain output. when cleared to 0, the pin functions as the cmos output. 5 wkp5 0 r/w this bit selects the function of pin p55/ wkp5 / adtrg . 0: general i/o port 1: wkp5 / adtrg input pin 4 wkp4 0 r/w this bit selects the function of pin p54/ wkp4 . 0: general i/o port 1: wkp4 input pin 3 wkp3 0 r/w this bit selects the function of pin p53/ wkp3 . 0: general i/o port 1: wkp3 input pin 2 wkp2 0 r/w this bit selects the function of pin p52/ wkp2 . 0: general i/o port 1: wkp2 input pin 1 wkp1 0 r/w this bit selects the function of pin p51/ wkp1 . 0: general i/o port 1: wkp1 input pin 0 wkp0 0 r/w this bit selects the function of pin p50/ wkp0 . 0: general i/o port 1: wkp0 input pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 124 of 472 rej09b0160-0200 9.4.2 port control register 5 (pcr5) pcr5 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 5 pins p57 to p50 functions as a general i/o port, setting a pcr5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.4.3 port data register 5 (pdr5) pdr5 is a general i/o port data register of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 5 pins. if pdr5 is read while pcr5 bi ts are set to 1, the value stored in pdr5 are read. if pdr5 is read while pcr5 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr5. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 125 of 472 rej09b0160-0200 9.4.4 port pull-up control register 5 (pucr5) pucr5 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 4 3 2 1 0 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w only bits for which pcr5 is cleared are valid. the pull-up mos of the corresponding pi ns enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 9.4.5 pin functions the correspondence between the register specification and the port functions is shown below. ? p57/scl pin register iccr1 pcr5 bit name ice pcr57 pin function setting value 0 0 p57 input pin 1 p57 output pin 1 x scl i/o pin [legend] x: don't care. scl performs the nmos open-drain output, that enables a direct bus drive. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 126 of 472 rej09b0160-0200 ? p56/sda pin register iccr1 pcr5 bit name ice pcr56 pin function setting value 0 0 p56 input pin 1 p56 output pin 1 x sda i/o pin [legend] x: don't care. sda performs the nmos open-drain output, that enables a direct bus drive. ? p55/ wkp5 / adtrg pin register pmr5 pcr5 bit name wkp5 pcr55 pin function setting value 0 0 p55 input pin 1 p55 output pin 1 x wkp5 / adtrg input pin [legend] x: don't care. ? p54/ wkp4 pin register pmr5 pcr5 bit name wkp4 pcr54 pin function setting value 0 0 p54 input pin 1 p54 output pin 1 x wkp4 input pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 127 of 472 rej09b0160-0200 ? p53/ wkp3 pin register pmr5 pcr5 bit name wkp3 pcr53 pin function setting value 0 0 p53 input pin 1 p53 output pin 1 x wkp3 input pin [legend] x: don't care. ? p52/ wkp2 pin register pmr5 pcr5 bit name wkp2 pcr52 pin function setting value 0 0 p52 input pin 1 p52 output pin 1 x wkp2 input pin [legend] x: don't care. ? p51/ wkp1 pin register pmr5 pcr5 bit name wkp1 pcr51 pin function setting value 0 0 p51 input pin 1 p51 output pin 1 x wkp1 input pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 128 of 472 rej09b0160-0200 ? p50/ wkp0 pin register pmr5 pcr5 bit name wkp0 pcr50 pin function setting value 0 0 p50 input pin 1 p50 output pin 1 x wkp0 input pin [legend] x: don't care. 9.5 port 6 port 6 is a general i/o port also functioning as a timer z i/o pin. each pin of the port 6 is shown in figure 9.5. the register setting of the timer z has priority for functions of the pins for both uses. p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 p60/ftioa0 port 6 figure 9.5 port 6 pin configuration port 6 has the following registers. ? port control register 6 (pcr6) ? port data register 6 (pdr6) section 9 i/o ports rev. 2.00 sep. 23, 2005 page 129 of 472 rej09b0160-0200 9.5.1 port control register 6 (pcr6) pcr6 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 6 pins p67 to p60 functions as a general i/o port, setting a pcr6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.5.2 port data register 6 (pdr6) pdr6 is a general i/o port data register of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 6 pins. if pdr6 is read while pcr6 bi ts are set to 1, the value stored in pdr6 are read. if pdr6 is read while pcr6 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr6. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 130 of 472 rej09b0160-0200 9.5.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p67/ftiod1 pin register toer tfcr tpmr tiorc1 pcr6 bit name ed1 cmd1 and cmd0 pwmd1 iod2 to iod0 pcr67 pin function setting value 1 00 0 0 p67 input/ftiod1 input pin 000 or 1xx 1 p67 output pin 0 00 0 001 or 01x x ftiod1 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? p66/ftioc1 pin register toer tfcr tpmr tiorc1 pcr6 bit name ec1 cmd1 and cmd0 pwmc1 ioc2 to ioc0 pcr66 pin function setting value 1 00 0 0 p66 input/ftioc1 input pin 000 or 1xx 1 p66 output pin 0 00 0 001 or 01x x ftioc1 output pin 1 xxx other than 00 x xxx [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 131 of 472 rej09b0160-0200 ? p65/ftiob1 pin register toer tfcr tpmr tiora1 pcr6 bit name eb1 cmd1 to cmd0 pwmb1 iob2 to iob0 pcr65 pin function setting value 1 00 0 0 p65 input/ftiob1 input pin 000 or 1xx 1 p65 output pin 0 00 0 001 or 01x x ftiob1 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? p64/ftioa1 pin register toer tfcr tiora1 pcr6 bit name eb1 cmd1 to cmd0 ioa2 to ioa0 pcr64 pin function setting value 1 xx 0 p64 input/ftioa1 input pin 000 or 1xx 1 p64 output pin 0 00 001 or 01x x ftioa1 output pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 132 of 472 rej09b0160-0200 ? p63/ftiod0 pin register toer tfcr tpmr tiorc0 pcr6 bit name ed0 cmd1 to cmd0 pwmd0 iod2 to iod0 pcr63 pin function setting value 1 00 0 0 p63 input/ftiod0 input pin 000 or 1xx 1 p63 output pin 0 00 0 001 or 01x x ftiod0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? p62/ftioc0 pin register toer tfcr tpmr tiorc0 pcr6 bit name ec0 cmd1 to cmd0 pwmc0 ioc2 to ioc0 pcr62 pin function setting value 1 00 0 0 p62 input/ftioc0 input pin 000 or 1xx 1 p62 output pin 0 00 0 001 or 01x x ftioc0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 133 of 472 rej09b0160-0200 ? p61/ftiob0 pin register toer tfcr tpmr tiora0 pcr6 bit name eb0 cmd1 to cmd0 pwmb0 iob2 to iob0 pcr61 pin function setting value 1 00 0 0 p61 input/ftiob0 input pin 000 or 1xx 1 p61 output pin 0 00 0 001 or 01x x ftiob0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? p60/ftioa0 pin register toer tfcr tfcr tiora0 pcr6 bit name ea0 cmd1 to cmd0 stclk ioa2 to ioa0 pcr60 pin function setting value 1 xx x 0 p60 input/ftioa0 input pin 000 or 1xx 1 p60 output pin 0 00 0 001 or 01x x ftioa0 output pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 134 of 472 rej09b0160-0200 9.6 port 7 port 7 is a general i/o port also functioning as a timer v i/o pin and sci3_2 i/o pin. each pin of the port 7 is shown in figure 9.6. the register settings of the timer v and sci3_2 have priority for functions of the pins for both uses. p76/tmov p75/tmciv p74/tmriv p72/txd_2 p71/rxd_2 p70/sck3_2 port 7 figure 9.6 port 7 pin configuration port 7 has the following registers. ? port control register 7 (pcr7) ? port data register 7 (pdr7) 9.6.1 port control register 7 (pcr7) pcr7 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ? pcr76 pcr75 pcr74 ? pcr72 pcr71 pcr70 ? 0 0 0 ? 0 0 0 ? w w w ? w w w when each of the port 7 pins p76 to p74 and p72 to p70 functions as a general i/o port, setting a pcr7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bits 7 and 3 are reserved bits. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 135 of 472 rej09b0160-0200 9.6.2 port data register 7 (pdr7) pdr7 is a general i/o port data register of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 ? p76 p75 p74 ? p72 p71 p70 1 0 0 0 1 0 0 0 ? r/w r/w r/w ? r/w r/w r/w stores output data for port 7 pins. if pdr7 is read while pcr7 bi ts are set to 1, the value stored in pdr7 are read. if pdr7 is read while pcr7 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr7. bits 7 and 3 are reserved bits. these bits are always read as 1. 9.6.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p76/tmov pin register tcsrv pcr7 bit name os3 to os0 pcr76 pin function setting value 0000 0 p76 input pin 1 p76 output pin other than the above values x tmov output pin [legend] x: don't care. ? p75/tmciv pin register pcr7 bit name pcr75 pin function setting value 0 p75 input/tmciv input pin 1 p75 output/tmciv input pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 136 of 472 rej09b0160-0200 ? p74/tmriv pin register pcr7 bit name pcr74 pin function setting value 0 p74 input/tmriv input pin 1 p74 output/tmriv input pin ? p72/txd_2 pin register pmr1 pcr7 bit name txd2 pcr72 pin function setting value 0 0 p72 input pin 1 p72 output pin 1 x txd_2 output pin [legend] x: don't care. ? p71/rxd_2 pin register scr3_2 pcr7 bit name re pcr71 pin function setting value 0 0 p71 input pin 1 p71 output pin 1 x rxd_2 input pin [legend] x: don't care. ? p70/sck3_2 pin register scr3_2 smr2 pcr7 bit name cke1 cke0 com pcr70 pin function setting value 0 0 0 0 p70 input pin 1 p70 output pin 0 0 1 x sck3_2 output pin 0 1 x x sck3_2 output pin 1 x x x sck3_2 input pin [legend] x: don't care. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 137 of 472 rej09b0160-0200 9.7 port 8 port 8 is a general i/o port. each pin of the port 8 is shown in figure 9.7. p87 p86 p85 port 8 figure 9.7 port 8 pin configuration port 8 has the following registers. ? port control register 8 (pcr8) ? port data register 8 (pdr8) 9.7.1 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 6 5 pcr87 pcr86 pcr85 0 0 0 w w w when each of the port 8 pins p87 to p85 functions as a general i/o port, setting a pcr8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 to 0 ? ? ? reserved section 9 i/o ports rev. 2.00 sep. 23, 2005 page 138 of 472 rej09b0160-0200 9.7.2 port data register 8 (pdr8) pdr8 is a general i/o port data register of port 8. bit bit name initial value r/w description 7 6 5 p87 p86 p85 0 0 0 r/w r/w r/w pdr8 stores output data for port 8 pins. if pdr8 is read while pcr8 bi ts are set to 1, the value stored in pdr8 is read. if pdr8 is read while pcr8 bits are cleared to 0, the pin stat es are read regardless of the value stored in pdr8. 4 to 0 ? all 1 ? reserved these bits are always read as 1. 9.7.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p87 pin register pcr8 bit name pcr87 pin function setting value 0 p87 input pin 1 p87 output pin ? p86 pin register pcr8 bit name pcr86 pin function setting value 0 p86 input pin 1 p86 output pin ? p85 pin register pcr8 bit name pcr85 pin function setting value 0 p85 input pin 1 p85 output pin section 9 i/o ports rev. 2.00 sep. 23, 2005 page 139 of 472 rej09b0160-0200 9.8 port b port b is an input port also functioning as an a/d converter analog input pin. each pin of the port b is shown in figure 9.8. pb7/an7 pb6/an6 pb5/an5 pb4/an4 pb3/an3 pb2/an2 pb1/an1 pb0/an0 port b figure 9.8 port b pin configuration port b has the following register. ? port data register b (pdrb) 9.8.1 port data register b (pdrb) pdrb is a general input-only port data register of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 ? ? ? ? ? ? ? ? r r r r r r r r the input value of each pin is read by reading this register. however, if a port b pin is designated as an analog input channel by adcsr in a/d converter, 0 is read. section 9 i/o ports rev. 2.00 sep. 23, 2005 page 140 of 472 rej09b0160-0200 section 10 realtime clock (rtc) rtc3000a_000120030300 rev. 2.00 sep. 23, 2005 page 141 of 472 rej09b0160-0200 section 10 realtime clock (rtc) the realtime clock (rtc) is a timer used to count time ranging from a second to a week. figure 10.1 shows the block diagram of the rtc. 10.1 features ? counts seconds, minutes, hours, and day-of-week ? start/stop function ? reset function ? readable/writable counter of seconds, minutes, hours, and day-of-week with bcd codes ? periodic (seconds, minutes, hours, days, and weeks) interrupts ? 8-bit free running counter ? selection of clock source section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 142 of 472 rej09b0160-0200 pss 32-khz oscillator circuit rtccsr rsecdr rmindr rwkdr clock count control circuit interrupt control circuit interrupt rtccr1 rhrdr rtccr2 internal data bus 1/4 tmow [legend] rtccsr: rsecdr: rmindr: rhrdr: rwkdr: rtccr1: rtccr2: pss: clock source select register second date register/free running counter data register minute date register hour date register day-of-week date register rtc control register 1 rtc control register 2 prescaler s figure 10.1 block diagram of rtc section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 143 of 472 rej09b0160-0200 10.2 input/output pin table 10.1 shows the rtc input/output pin. table 10.1 pin configuration name abbreviation i/o function clock output tmow output rtc divided clock output 10.3 register descriptions the rtc has the following registers. ? second data register/free running counter data register (rsecdr) ? minute data register (rmindr) ? hour data register (rhrdr) ? day-of-week data register (rwkdr) ? rtc control register 1 (rtccr1) ? rtc control register 2 (rtccr2) ? clock source select register (rtccsr) 10.3.1 second data register/free runn ing counter data register (rsecdr) rsecdr counts the bcd-coded second value. the setti ng range is decimal 00 to 59. it is an 8-bit read register used as a counter, when it operates as a free running counter. for more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, data reading procedure. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 sc12 sc11 sc10 ? ? ? r/w r/w r/w counting ten?s position of seconds counts on 0 to 5 for 60-second counting. section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 144 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 2 1 0 sc03 sc02 sc01 sc00 ? ? ? ? r/w r/w r/w r/w counting one?s position of seconds counts on 0 to 9 once per second. when a carry is generated, 1 is added to the ten?s position. 10.3.2 minute data register (rmindr) rmindr counts the bcd-coded minute value on the carry generated once per minute by the rsecdr counting. the setting range is decimal 00 to 59. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 mn12 mn11 mn10 ? ? ? r/w r/w r/w counting ten?s position of minutes counts on 0 to 5 for 60-minute counting. 3 2 1 0 mn03 mn02 mn01 mn00 ? ? ? ? r/w r/w r/w r/w counting one?s position of minutes counts on 0 to 9 once per minute. when a carry is generated, 1 is added to the ten?s position. section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 145 of 472 rej09b0160-0200 10.3.3 hour data register (rhrdr) rhrdr counts the bcd-coded hour value on the carry generated once per hour by rmindr. the setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in rtccr1. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 ? 0 ? reserved this bit is always read as 0. 5 4 hr11 hr10 ? ? r/w r/w counting ten?s position of hours counts on 0 to 2 for ten?s position of hours. 3 2 1 0 hr03 hr02 hr01 hr00 ? ? ? ? r/w r/w r/w r/w counting one?s position of hours counts on 0 to 9 once per hour. when a carry is generated, 1 is added to the ten?s position. section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 146 of 472 rej09b0160-0200 10.3.4 day-of-week data register (rwkdr) rwkdr counts the bcd-coded day-of-week value on the carry generated once per day by rhrdr. the setting range is decimal 0 to 6 using bits wk2 to wk0. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 to 3 ? all 0 ? reserved these bits are always read as 0. 2 1 0 wk2 wk1 wk0 ? ? ? r/w r/w r/w day-of-week counting day-of-week is indicated with a binary code 000: sunday 001: monday 010: tuesday 011: wednesday 100: thursday 101: friday 110: saturday 111: reserved (setting prohibited) section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 147 of 472 rej09b0160-0200 10.3.5 rtc control register 1 (rtccr1) rtccr1 controls start/stop and reset of the clock timer. for the definition of time expression, see figure 10.2. bit bit name initial value r/w description 7 run ? r/w rtc operation start 0: stops rtc operation 1: starts rtc operation 6 12/24 ? r/w operating mode 0: rtc operates in 12-hour mode. rhrdr counts on 0 to 11. 1: rtc operates in 24-hour mode. rhrdr counts on 0 to 23. 5 pm ? r/w a.m./p.m. 0: indicates a.m. when rtc is in the 12-hour mode. 1: indicates p.m. when rtc is in the 12-hour mode. 4 rst 0 r/w reset 0: normal operation 1: resets registers and control circuits except rtccsr and this bit. clear this bit to 0 after having been set to 1. 3 to 0 ? all 0 ? reserved these bits are always read as 0. 24-hour count 01234567891011121314151617 12-hour count 0 pm 24-hour count 12-hour count pm 0 (morning) 1 (afternoon) noon 123456789101101234 5 18 19 20 21 22 23 0 6 1 (afternoon) 0 7 8 9 10 11 0 figure 10.2 definition of time expression section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 148 of 472 rej09b0160-0200 10.3.6 rtc control register 2 (rtccr2) rtccr2 controls rtc periodic interrupts of weeks, days, hours, minutes, and seconds. enabling interrupts of weeks, days, hours, minutes, and seconds sets the irrta flag to 1 in the interrupt flag register 1 (irr1) when an interrupt occurs. it also controls an overflow interrupt of a free running counter when rtc operat es as a free running counter. bit bit name initial value r/w description 7, 6 ? all 0 ? reserved these bits are always read as 0. 5 foie ? r/w free running counter overflow interrupt enable 0: disables an overflow interrupt 1: enables an overflow interrupt 4 wkie ? r/w week periodic interrupt enable 0: disables a week periodic interrupt 1: enables a week periodic interrupt 3 dyie ? r/w day periodic interrupt enable 0: disables a day periodic interrupt 1: enables a day periodic interrupt 2 hrie ? r/w hour periodic interrupt enable 0: disables an hour periodic interrupt 1: enables an hour periodic interrupt 1 mnie ? r/w minute periodic interrupt enable 0: disables a minute periodic interrupt 1: enables a minute periodic interrupt 0 seie ? r/w second peri odic interrupt enable 0: disables a second periodic interrupt 1: enables a second periodic interrupt section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 149 of 472 rej09b0160-0200 10.3.7 clock source sel ect register (rtccsr) rtccsr selects clock source. a free running counter controls start/stop of counter operation by the run bit in rtccr1. when a clock other than 32.768 khz is selected, the rtc is disabled and operates as an 8-b it free running counter. when the rtc operates as an 8-bit free running counter, rsecdr enables counter values to be read. an interrupt can be generated by setting 1 to the foie bit in rtccr2 and enabling an overflow interrupt of the free running counter. a clock in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 5 rcs6 rcs5 0 0 r/w r/w clock output selection selects a clock output from the tmow pin when setting tmow in pmr1 to 1. 00: /4 01: /8 10: /16 11: /32 4 ? 0 ? reserved this bit is always read as 0. 3 2 1 0 rcs3 rcs2 rcs1 rcs0 1 0 0 0 r/w r/w r/w r/w clock source selection 0000: /8 ?????????????????? free running counter operation 0001: /32 ???????????????? free running counter operation 0010: /128 ?????????????? free running counter operation 0011: /256 ?????????????? free running counter operation 0100: /512 ?????????????? free running counter operation 0101: /2048 ???????????? free running counter operation 0110: /4096 ???????????? free running counter operation 0111: /8192 ???????????? free running counter operation 1xxx: 32.768 khz ????? rtc operation [legend] x: don't care. section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 150 of 472 rej09b0160-0200 10.4 operation 10.4.1 initial settings of registers after power-on the rtc registers that store s econd, minute, hour, and day-of week data are not reset by a res input. therefore, all registers must be set to thei r initial values after powe r-on. once the register setting are made, the rtc provides an accurate time as long as power is su pplied regardless of a res input. 10.4.2 initial setting procedure figure 10.3 shows the procedure for the initial se tting of the rtc. to set the rtc again, also follow this procedure. rtc operation is stopped. rtc registers and clock count controller are reset. clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, and a.m/p.m are set. rtc operation is started. run in rtccr1 = 0 rst in rtccr1 = 1 rst in rtccr1 = 0 set rtccsr, rsecdr, rmindr, rhrdr, rwkdr, 12/24 in rtccr1, and pm run in rtccr1 = 1 figure 10.3 initia l setting procedure section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 151 of 472 rej09b0160-0200 10.4.3 data reading procedure when the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be corr ect, and so the time data must be read again. figure 10.4 shows an example in which correct data is not obtained. in this exampl e, since only rsecdr is read after data update, about 1-minute inconsistency occurs. to avoid reading in this timing, the following processing must be performed. 1. check the setting of the bsy bit, and when the bsy bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. when about 62.5 ms is passed after the bsy bit is set to 1, the registers are updated, and the bsy bit is cleared to 0. 2. making use of interrupts, read from the second, minute, hour, and day-of week registers after the irrta flag in irr1 is set to 1 and the bsy bit is confirmed to be 0. 3. read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used. before update rwkdr = h'03, rhddr = h'13, rmindr = h'46, rsecdr = h'59 bsy bit = 0 (1) day-of-week data register read h'03 (2) hour data register read h'13 (3) minute data register read h'46 bsy bit -> 1 (under data update) after update rwkdr = h'03, rhddr = h'13, rmindr = h'47, rsecdr = h'00 bsy bit -> 0 (4) second data register read h'00 processing flow figure 10.4 example: readin g of inaccurate time data section 10 realtime clock (rtc) rev. 2.00 sep. 23, 2005 page 152 of 472 rej09b0160-0200 10.5 interrupt source there are five kinds of rtc interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. when using an interrupt, initiate the rtc last af ter other registers are set. do not set multiple interrupt enable bits in rtccr2 simultaneously to 1. when an interrupt request of the rtc occurs, the i rrta flag in irr1 is se t to 1. when clearing the flag, write 0. table 10.2 interrupt source interrupt name interrupt s ource interrupt enable bit overflow interrupt occurs when the free running counter is overflown. foie week periodic interrupt occurs every week when the day-of-week date register value becomes 0. wkie day periodic interrupt occurs every day when the day-of-week date register is counted. dyie hour periodic interrupt occurs ever y hour when the hour date register is counted. hrie minute periodic interrupt occurs every minute when the minute date register is counted. mnie second periodic interrupt occurs every second when the second date register is counted. scie section 11 timer b1 tim08b0a_000020020200 rev. 2.00 sep. 23, 2005 page 153 of 472 rej09b0160-0200 section 11 timer b1 timer b1 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operating modes, interval and auto reload. figure 11.1 shows a block diagram of timer b1. 11.1 features ? selection of seven internal clock sources ( /8192, /2048, /512, /256, /64, /16, and /4) or an external clock (can be used to count external events). ? an interrupt is generated when the counter overflows. [legend] tmb1: tmib1 tcb1: timer mode register b1 timer counter b1 tlb1: irrtb1: timer load register b1 timer b1 interrupt request flag pss: tmib1: prescaler s timer b1 event input internal data bus tcb1 tmb1 pss tlb1 irrtb1 figure 11.1 block diagram of timer b1 section 11 timer b1 rev. 2.00 sep. 23, 2005 page 154 of 472 rej09b0160-0200 11.2 input/output pin table 11.1 shows the timer b1 pin configuration. table 11.1 pin configuration name abbreviation i/o function timer b1 event input tmib1 input event input to tcb1 11.3 register descriptions the timer b1 has the following registers. ? timer mode register b1 (tmb1) ? timer counter b1 (tcb1) ? timer load register b1 (tlb1) 11.3.1 timer mode register b1 (tmb1) tmb1 selects the auto-reload function and input clock. bit bit name initial value r/w description 7 tmb17 0 r/w auto-reload function select 0: interval timer function selected 1: auto-reload function selected 6 to 3 ? all 1 ? reserved these bits are always read as 1. section 11 timer b1 rev. 2.00 sep. 23, 2005 page 155 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 1 0 tmb12 tmb11 tmb10 0 0 0 r/w r/w r/w clock select 000: internal clock: /8192 001: internal clock: /2048 010: internal clock: /512 011: internal clock: /256 100: internal clock: /64 101: internal clock: /16 110: internal clock: /4 111: external event (tmib1): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the interrupt edge select register 1 (iegr1). see section 3.2.1, interrupt edge select register 1 (iegr1), for details. before setting tmb12 to tmb10 to 1, irq1 in the port mode register 1 (pmr1) should be set to 1. 11.3.2 timer coun ter b1 (tcb1) tcb1 is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by b its tmb12 to tmb10 in tmb1. tcb1 values can be read by the cpu at any time. when tcb1 overflows from h'ff to h'00 or to the value set in tlb1, the irrtb1 flag in irr2 is set to 1. tcb1 is allocated to the same address as tlb1. tcb1 is initialized to h'00. 11.3.3 timer load register b1 (tlb1) tlb1 is an 8-bit write-only register for setting the reload value of tcb1. when a reload value is set in tlb1, the same value is loaded into tcb1 as well, and tcb1 starts counting up from that value. when tcb1 overflows during operation in auto-reload mode, the tlb1 value is loaded into tcb1. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. tlb1 is allocated to the same address as tcb1. tlb1 is initialized to h'00. section 11 timer b1 rev. 2.00 sep. 23, 2005 page 156 of 472 rej09b0160-0200 11.4 operation 11.4.1 interval timer operation when bit tmb17 in tmb1 is cleared to 0, timer b1 functions as an 8-bit interval timer. upon reset, tcb1 is cleared to h'00 and bit tmb17 is cleared to 0, so up-counting and interval timing resume immediately. the operating clock of tim er b1 is selected from seven internal clock signals output by prescaler s, or an external clock input at pin tmb1. the selection is made by bits tmb12 to tmb10 in tmb1. after the count value in tmb1 r eaches h'ff, the next clock sign al input causes timer b1 to overflow, setting flag irrtb1 in irr2 to 1. if ient b1 in ienr2 is 1, an interrupt is requested to the cpu. at overflow, tcb1 returns to h'00 and starts counting up again. during interval timer operation (tmb17 = 0), when a value is set in tlb1, the same value is set in tcb1. 11.4.2 auto-reloa d timer operation setting bit tmb17 in tmb1 to 1 causes timer b1 to function as an 8-bit auto-reload timer. when a reload value is set in tlb1, the same value is loaded into tcb1, becoming the value from which tcb1 starts its count. after the count value in tcb1 reaches h'ff, the next clock signal input causes timer b1 to overflow. the tlb1 value is then loaded into tcb1, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb1 value. the clock sources and interrupts in auto-reload mo de are the same as in interval mode. in auto- reload mode (tmb17 = 1), when a new value is set in tlb1, the tlb1 value is also loaded into tcb1. 11.4.3 event counter operation timer b1 can operate as an event counter in which tmib1 is set to an event input pin. external event counting is selected by setting bits tmb12 to tmb10 in tmb1 to 1. tcb1 counts up at rising or falling edge of an external event signal input at pin tmb1. when timer b1 is used to count external event input, bit irq1 in pmr1 should be set to 1 and ien1 in ienr1 should be cleared to 0 to disable irq1 interrupt requests. section 11 timer b1 rev. 2.00 sep. 23, 2005 page 157 of 472 rej09b0160-0200 11.5 timer b1 operating modes table 11.2 shows the timer b1 operating modes. table 11.2 timer b1 operating modes operating mode reset active sleep subactive subsleep standby interval reset functions f unctions halted halted halted tcb1 auto-reload reset functions f unctions halted halted halted tmb1 reset functions retained retained retained retained section 11 timer b1 rev. 2.00 sep. 23, 2005 page 158 of 472 rej09b0160-0200 section 12 timer v tim08v0a_000120030300 rev. 2.00 sep. 23, 2005 page 159 of 472 rej09b0160-0200 section 12 timer v timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. figure 12.1 shows a block diagram of timer v. 12.1 features ? choice of seven clock signals is available. choice of six internal clock sources ( /128, /64, /32, /16, /8, /4) or an external clock. ? counter can be cleared by compare match a or b, or by an external reset signal. if the count stop function is selected, the co unter can be halted when cleared. ? timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, pwm output, and other applications. ? three interrupt sources: compare matc h a, compare match b, timer overflow ? counting can be initiated by trigger input at the trgv pin. the rising edge, falling edge, or both edges of the trgv input can be selected. section 12 timer v rev. 2.00 sep. 23, 2005 page 160 of 472 rej09b0160-0200 trgv tmciv tmriv tmov trigger control clock select clear control output control pss tcrv1 tcorb comparator tcntv comparator tcora tcrv0 interrupt request control tcsrv cmia cmib ovi internal data bus [legend] tcora: time constant register a tcorb: time constant register b tcntv: timer counter v tcsrv: timer control/status register v tcrv0: timer control register v0 tcrv1: timer control register v1 pss: prescaler s cmia: compare-match interrupt a cmib: compare-match interrupt b ovi: overflow interupt figure 12.1 block diagram of timer v section 12 timer v rev. 2.00 sep. 23, 2005 page 161 of 472 rej09b0160-0200 12.2 input/output pins table 12.1 shows the timer v pin configuration. table 12.1 pin configuration name abbreviation i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting 12.3 register descriptions time v has the following registers. ? timer counter v (tcntv) ? timer constant register a (tcora) ? timer constant register b (tcorb) ? timer control register v0 (tcrv0) ? timer control/status register v (tcsrv) ? timer control register v1 (tcrv1) 12.3.1 timer counter v (tcntv) tcntv is an 8-bit up-counter. the clock source is selected by bits cks2 to cks0 in timer control register v0 (tcrv0). the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset in put signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows, ovf is set to 1 in timer control/status register v (tcsrv). tcntv is initialized to h'00. section 12 timer v rev. 2.00 sep. 23, 2005 page 162 of 472 rej09b0160-0200 12.3.2 time constant registers a and b (tcora, tcorb) tcora and tcorb have the same function. tcora and tcorb are 8-bit read/write registers. tcora and tcntv are compared at all times. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also se t to 1 in tcrv0, a cpu interrupt is requested. note that they must not be compared duri ng the t3 state of a tcora write cycle. timer output from the tmov pin can be controlled by the identifying signal (compare match a) and the settings of bits os3 to os0 in tcsrv. tcora and tcorb are initialized to h'ff. 12.3.3 timer control register v0 (tcrv0) tcrv0 selects the input clock signals of tcntv, specifies the clearing conditions of tcntv, and controls each interrupt request. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b when this bit is set to 1, interrupt request from the cmfb bit in tcsrv is enabled. 6 cmiea 0 r/w compare match interrupt enable a when this bit is set to 1, interrupt request from the cmfa bit in tcsrv is enabled. 5 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, interrupt request from the ovf bit in tcsrv is enabled. section 12 timer v rev. 2.00 sep. 23, 2005 page 163 of 472 rej09b0160-0200 bit bit name initial value r/w description 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits specify the clear ing conditions of tcntv. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared on the rising edge of the tmriv pin. the operation of tcntv after clearing depends on trge in tcrv1. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select clock signals to input to tcntv and the counting condition in combination with icks0 in tcrv1. refer to table 12.2. table 12.2 clock signals to input to tcntv and counting conditions tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 0 0 0 ? clock input prohibited 1 0 internal clock: counts on /4, falling edge 1 internal clock: counts on /8, falling edge 1 0 0 internal clock: counts on /16, falling edge 1 internal clock: counts on /32, falling edge 1 0 internal clock: counts on /64, falling edge 1 internal clock: counts on /128, falling edge 1 0 0 ? clock input prohibited 1 ? external clock: counts on rising edge 1 0 ? external clock: counts on falling edge 1 ? external clock: counts on rising and falling edge section 12 timer v rev. 2.00 sep. 23, 2005 page 164 of 472 rej09b0160-0200 12.3.4 timer control/st atus register v (tcsrv) tcsrv indicates the status flag and controls outputs by using a compare match. bit bit name initial value r/w description 7 cmfb 0 r/w compare match flag b setting condition: when the tcntv value matches the tcorb value clearing condition: after reading cmfb = 1, cleared by writing 0 to cmfb 6 cmfa 0 r/w compare match flag a setting condition: when the tcntv value matches the tcora value clearing condition: after reading cmfa = 1, cleared by writing 0 to cmfa 5 ovf 0 r/w timer overflow flag setting condition: when tcntv overflows from h'ff to h'00 clearing condition: after reading ovf = 1, cleared by writing 0 to ovf 4 ? 1 ? reserved this bit is always read as 1. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select an output method for the tmov pin by the compare match of tcorb and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles section 12 timer v rev. 2.00 sep. 23, 2005 page 165 of 472 rej09b0160-0200 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select an output method for the tmov pin by the compare match of tcora and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two output levels can be controlled independently. after a reset, the timer output is 0 until the first compare match. 12.3.5 timer control register v1 (tcrv1) tcrv1 selects the edge at the trgv pin, enab les trgv input, and selects the clock input to tcntv. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 tveg1 tveg0 0 0 r/w r/w trgv input edge select these bits select the trgv input edge. 00: trgv trigger input is prohibited 01: rising edge is selected 10: falling edge is selected 11: rising and falling edges are both selected 2 trge 0 r/w tcnt starts counting up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. section 12 timer v rev. 2.00 sep. 23, 2005 page 166 of 472 rej09b0160-0200 bit bit name initial value r/w description 1 ? 1 ? reserved this bit is always read as 1. 0 icks0 0 r/w internal clock select 0 this bit selects clock sign als to input to tcntv in combination with cks2 to cks0 in tcrv0. refer to table 12.2. 12.4 operation 12.4.1 timer v operation 1. according to table 12.2, six internal/external clock signals output by prescaler s can be selected as the timer v operating clock signals . when the operating cl ock signal is selected, tcntv starts counting-up. figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2. when tcntv overflows (changes from h'ff to h'00), the overflow flag (ovf) in tcrv0 will be set. the timing at this time is shown in fi gure 12.4. an interrupt request is sent to the cpu when ovie in tcrv0 is 1. 3. tcntv is constantly compared with tcora and tcorb. compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv ma tches tcora or tcorb, respectively. the compare-match signal is generated in the last state in which the values match. figure 12.5 shows the timing. an interrupt request is generated for the cpu when cmiea or cmieb in tcrv0 is 1. 4. when a compare match a or b is generated, the tmov responds with the output value selected by bits os3 to os0 in tcsrv. figure 12.6 shows the timing when the output is toggled by compare match a. 5. when cclr1 or cclr0 in tcrv0 is 01 or 10, tcntv can be cleared by the corresponding compare match. figure 12.7 shows the timing. 6. when cclr1 or cclr0 in tcrv0 is 11, tcnt v can be cleared by the rising edge of the input of tmriv pin. a tmriv input pulse-width of at least 1.5 system clocks is necessary. figure 12.8 shows the timing. 7. when a counter-clearing source is generated with trge in tcrv1 set to 1, the counting-up is halted as soon as tcntv is cleared. tcntv resu mes counting-up when the edge selected by tveg1 or tveg0 in tcrv1 is input from the tgrv pin. section 12 timer v rev. 2.00 sep. 23, 2005 page 167 of 472 rej09b0160-0200 n ? 1 n + 1 n internal clock tcntv input clock tcntv figure 12.2 increment timi ng with internal clock n ? 1 n + 1 n tmciv (external clock input pin) tcntv input clock tcntv figure 12.3 increment timing with external clock h'ff h'00 tcntv overflow signal ovf figure 12.4 ovf set timing section 12 timer v rev. 2.00 sep. 23, 2005 page 168 of 472 rej09b0160-0200 n n n+1 tcntv tcora or tcorb compare match signal cmfa or cmfb figure 12.5 cmfa and cmfb set timing compare match a signal timer v output pin figure 12.6 tmov output timing n h'00 compare match a signal tcntv figure 12.7 clear ti ming by compare match section 12 timer v rev. 2.00 sep. 23, 2005 page 169 of 472 rej09b0160-0200 tmriv (external counter reset input pin) tcntv reset signal tcntv n ? 1 n h'00 figure 12.8 clear ti ming by tmriv input 12.5 timer v application examples 12.5.1 pulse output with arbitrary duty cycle figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcora. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 4. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. counter cleared time tcntv value h'ff tcora tcorb h'00 tmov figure 12.9 pulse output example section 12 timer v rev. 2.00 sep. 23, 2005 page 170 of 472 rej09b0160-0200 12.5.2 pulse output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 12.10. to set up this output: 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits tveg1 and tveg0 in tcrv1 and set trge to select the falling edge of the trgv input. 4. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 5. after these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb ? tcora). counter cleared h'ff tcora tcorb h'00 trgv tmov compare match a compare match b clears tcntv and halts count-up compare match b clears tcntv and halts count-up compare match a tcntv value time figure 12.10 example of pulse ou tput synchronized to trgv input section 12 timer v rev. 2.00 sep. 23, 2005 page 171 of 472 rej09b0160-0200 12.6 usage notes the following types of contention or operation can occur in timer v operation. 1. writing to registers is performed in the t3 state of a tcntv write cycle. if a tcntv clear signal is generated in the t3 state of a tcntv write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. if counting-up is generated in the t3 state of a tcntv write cy cle, writing takes precedence. 2. if a compare match is generated in the t3 st ate of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 12.12 shows the timing. 3. if compare matches a and b occur simultaneously, any conflict between the output selections for compare match a and compare match b is re solved by the following priority: toggle output > output 1 > output 0. 4. depending on the timing, tcntv may be incremented by a switch between different internal clock sources. when tcntv is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock ( ). therefore, as shown in figure 12.3 the switch is from a high cloc k signal to a low clock signal, the switchover is seen as a falling edge, causing tcntv to incr ement. tcntv can also be incremented by a switch between internal and external clocks. address tcntv address tcntv write cycle by cpu internal write signal counter clear signal tcntv n h'00 t 1 t 2 t 3 figure 12.11 contention between tcntv write and clear section 12 timer v rev. 2.00 sep. 23, 2005 page 172 of 472 rej09b0160-0200 address tcora address internal write signal tcntv tcora n n n+1 m tcora write data inhibited t 1 t 2 t 3 tcora write cycle by cpu compare match signal figure 12.12 contention betwee n tcora write and compare match clock before switching clock after switching count clock tcntv n n+1 n+2 write to cks1 and cks0 figure 12.13 internal clock switching and tcntv operation section 13 timer z tim08z0a_000120030300 rev. 2.00 sep. 23, 2005 page 173 of 472 rej09b0160-0200 section 13 timer z the timer z has a 16-bit timer with two channels. figures 13.1, 13.2, and 13.3 show the block diagrams of entire timer z, its channel 0, and its channel 1, respectively. for details on the timer z functions, refer to table 13.1. 13.1 features ? capability to process up to eight inputs/outputs ? eight general registers (gr): fo ur registers for each channel ? independently assignable output compare or input capture functions ? selection of five counter clock sources: four internal clocks ( , /2, /4, and /8) and an external clock ? seven selectable operating modes ? output compare function selection of 0 output, 1 output, or toggle output ? input capture function rising edge, falling edge, or both edges ? synchronous operation timer counters_0 and _1 (tcnt_0 and tcnt_1) can be written simultaneously. simultaneous clearing by compare match or input capture is possible. ? pwm mode up to six-phase pwm output can be provided with desired duty ratio. ? reset synchronous pwm mode three-phase pwm output for normal and counter phases ? complementary pwm mode three-phase pwm output for non-overlapped normal and counter phases the a/d conversion start trigger can be set for pwm cycles. ? buffer operation the input capture register can be consisted of double buffers. the output compare register can automatically be modified. ? high-speed access by th e internal 16-bit bus ? 16-bit tcnt and gr registers can be accesse d in high speed by a 16-bit bus interface ? any initial timer output value can be set ? output of the timer is disabled by external trigger section 13 timer z rev. 2.00 sep. 23, 2005 page 174 of 472 rej09b0160-0200 ? eleven interr upt sources ? four compare match/input capture interrupts and an overflow interrupt are available for each channel. an underflow interr upt can be set for channel 1. table 13.1 timer z functions item channel 0 channel 1 count clock internal clocks: , /2, /4, /8 external clock: ftioa0 (tclk) general registers (output compare/input capture registers) gra_0, grb_0, grc_0, grd_0 gra_1, grb_1, grc_1, grd_1 buffer register grc_0, grd_0 grc_1, grd_1 i/o pins ftioa0, ftiob0, ftioc0, ftiod0 ftioa1, ftiob1, ftioc1, ftiod1 counter clearing function com pare match/input capture of gra_0, grb_0, grc_0, or grd_0 compare match/input capture of gra_1, grb_1, grc_1, or grd_1 0 output yes yes 1 output yes yes compare match output output yes yes input capture function yes yes synchronous operation yes yes pwm mode yes yes reset synchronous pwm mode yes yes complementary pwm mode yes yes buffer function yes yes interrupt sources compare match/input capture a0 to d0 overflow compare match/input capture a1 to d1 overflow underflow section 13 timer z rev. 2.00 sep. 23, 2005 page 175 of 472 rej09b0160-0200 itmz0 ftioa0 itmz1 adtrg channel 0 timer channel 1 timer module data bus ftiob0 ftioc0 ftiod0 ftioa1 ftiob1 ftioc1 ftiod1 tstr: [legend] tmdr: tfcr: toer: tocr: adtrg : itmz0: itmz1: timer start register (8 bits) timer mode register (8 bits) tpmr: timer pwm mode register (8 bits) timer function control register (8 bits) timer output master enable register (8 bits) timer output control register (8 bits) a/d conversion start trigger output signal channel 0 interrupt channel 1 interrupt toer tocr tpmr tfcr tstr tmdr control logic , /2, /4, /8 figure 13.1 timer z block diagram section 13 timer z rev. 2.00 sep. 23, 2005 page 176 of 472 rej09b0160-0200 itmz0 ftiod0 ftioc0 ftiob0 ftioa0 tcnt_0 gra_0 grb_0 grc_0 grd_0 tcr_0 tiora_0 tsr_0 tiorc_0 tier_0 pocr_0 tcnt_0: gra_0, grb_0: grc_0, grd_0 : tcr_0: tiora_0: tier_0: tsr_0: itmz0: timer counter_0 (16 bits) general registers a_0, b_0, c_0, and d_0 (input capture/output compare registers: 16 bits 4) timer control register_0 (8 bits) timer i/o control register a_0 (8 bits) tiorc_0: timer i/o control register c_0 (8 bits) timer interrupt enable register_0 (8 bits) pocr_0: pwm mode output level control register_0 (8 bits) timer status register_0 (8 bits) channel 0 interrupt [legend] , /2, /4, /8 clock select control logic module data bus comparator figure 13.2 timer z (channel 0) block diagram section 13 timer z rev. 2.00 sep. 23, 2005 page 177 of 472 rej09b0160-0200 itmz1 ftiod1 ftioc1 ftiob1 ftioa1 tcnt_1 gra_1 grb_1 grc_1 grd_1 tcr_1 tiora_1 tsr_1 tiorc_1 tier_1 pocr_1 tcnt_1: gra_1, grb_1: grc_1, grd_1: tcr_1: tiora_1: tier_1: tsr_1: itmz1: timer counter_1 (16 bits) general registers a_1, b_1, c_1, and d_1 (input capture/output compare registers: 16 bits 4) timer control register_1 (8 bits) timer i/o control register a_1 (8 bits) tiorc_1: timer i/o control register c_1 (8 bits) timer interrupt enable register_1 (8 bits) pocr_1: pwm mode output level control register_1 (8 bits) timer status register_1 (8 bits) channel 1 interrupt [legend] , /2, /4, /8 clock select control logic module data bus comparator figure 13.3 timer z (channel 1) block diagram section 13 timer z rev. 2.00 sep. 23, 2005 page 178 of 472 rej09b0160-0200 13.2 input/output pins table 13.2 summarizes the timer z pins. table 13.2 pin configuration name abbreviation input/output function input capture/output compare a0 ftioa0 input/output gra_0 output compare output, gra_0 input capture input, or external clock input (tclk) input capture/output compare b0 ftiob0 input/output grb_0 output compare output, grb_0 input capture input, or pwm output input capture/output compare c0 ftioc0 input/output grc_0 ou tput compare output, grc_0 input capture input, or pwm synchronous output (in reset synchronous pwm and complementary pwm modes) input capture/output compare d0 ftiod0 input/output grd_0 ou tput compare output, grd_0 input capture input, or pwm output input capture/output compare a1 ftioa1 input/output gra_1 output compare output, gra_1 input capture input, or pwm output (in reset synchronous pwm and complementary pwm modes) input capture/output compare b1 ftiob1 input/output grb_1 output compare output, grb_1 input capture input, or pwm output input capture/output compare c1 ftioc1 input/output grc_1 ou tput compare output, grc_1 input capture input, or pwm output input capture/output compare d1 ftiod1 input/output grd_1 ou tput compare output, grd_1 input capture input, or pwm output section 13 timer z rev. 2.00 sep. 23, 2005 page 179 of 472 rej09b0160-0200 13.3 register descriptions the timer z has the following registers. common ? timer start register (tstr) ? timer mode register (tmdr) ? timer pwm mode register (tpmr) ? timer function control register (tfcr) ? timer output master enable register (toer) ? timer output control register (tocr) channel 0 ? timer control register_0 (tcr_0) ? timer i/o control register a_0 (tiora_0) ? timer i/o control register c_0 (tiorc_0) ? timer status register_0 (tsr_0) ? timer interrupt enable register_0 (tier_0) ? pwm mode output level control register_0 (pocr_0) ? timer counter_0 (tcnt_0) ? general register a_0 (gra_0) ? general register b_0 (grb_0) ? general register c_0 (grc_0) ? general register d_0 (grd_0) channel 1 ? timer control register_1 (tcr_1) ? timer i/o control register a_1 (tiora_1) ? timer i/o control register c_1 (tiorc_1) ? timer status register_1 (tsr_1) ? timer interrupt enable register_1 (tier_1) ? pwm mode output level control register_1 (pocr_1) ? timer counter_1 (tcnt_1) ? general register a_1 (gra_1) ? general register b_1 (grb_1) section 13 timer z rev. 2.00 sep. 23, 2005 page 180 of 472 rej09b0160-0200 ? general register c_1 (grc_1) ? general register d_1 (grd_1) 13.3.1 timer start register (tstr) tstr selects the operation/stop for the tcnt counter. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 1 str1 0 r/w channel 1 counter start 0: tcnt_1 halts counting 1: tcnt_1 starts counting 0 str0 0 r/w channel 0 counter start 0: tcnt_0 halts counting 1: tcnt_0 starts counting 13.3.2 timer mode register (tmdr) tmdr selects buffer operation settin gs and synchronized operation. bit bit name initial value r/w description 7 bfd1 0 r/w buffer operation d1 0: grd_1 operates normally 1: grb_1 and grd_1 are used together for buffer operation 6 bfc1 0 r/w buffer operation c1 0: grc_1 operates normally 1: gra_1 and grd_1 are used together for buffer operation 5 bfd0 0 r/w buffer operation d0 0: grd_0 operates normally 1: grb_0 and grd_0 are used together for buffer operation section 13 timer z rev. 2.00 sep. 23, 2005 page 181 of 472 rej09b0160-0200 bit bit name initial value r/w description 4 bfc0 0 r/w buffer operation c0 0: grc_0 operates normally 1: gra_0 and grc_0 are used together for buffer operation 3 to 1 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 0 sync 0 r/w timer synchronization 0: tcnt_1 and tcnt_0 operat e as a different timer 1: tcnt_1 and tcnt_0 are synchronized tcnt_1 and tcnt_0 can be pre-set or cleared synchronously 13.3.3 timer pwm mode register (tpmr) tpmr sets the pin to enter pwm mode. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 6 pwmd1 0 r/w pwm mode d1 0: ftiod1 operates normally 1: ftiod1 operates in pwm mode 5 pwmc1 0 r/w pwm mode c1 0: ftioc1 operates normally 1: ftioc1 operates in pwm mode 4 pwmb1 0 r/w pwm mode b1 0: ftiob1 operates normally 1: ftiob1 operates in pwm mode 3 ? 1 ? reserved this bit is always read as 1, and cannot be modified. section 13 timer z rev. 2.00 sep. 23, 2005 page 182 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 pwmd0 0 r/w pwm mode d0 0: ftiod0 operates normally 1: ftiod0 operates in pwm mode 1 pwmc0 0 r/w pwm mode c0 0: ftioc0 operates normally 1: ftioc0 operates in pwm mode 0 pwmb0 0 r/w pwm mode b0 0: ftiob0 operates normally 1: ftiob0 operates in pwm mode 13.3.4 timer function control register (tfcr) tfcr selects the settings and output levels for each operating mode. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 stclk 0 r/w external clock input select 0: external clock input is disabled 1: external clock input is enabled 5 adeg 0 r/w a/d trigger edge select a/d module should be set to start an a/d conversion by the external trigger 0: a/d trigger at the crest in complementary pwm mode 1: a/d trigger at the trough in complementary pwm mode 4 adtrg 0 r/w external trigger disable 0: a/d trigger for pwm cycles is disabled in complementary pwm mode 1: a/d trigger for pwm cycles is enabled in complementary pwm mode section 13 timer z rev. 2.00 sep. 23, 2005 page 183 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 ols1 0 r/w output level select 1 selects the counter-phase output levels in reset synchronous pwm mode or complementary pwm mode. 0: initial output is high and the active level is low. 1: initial output is low and the active level is high. 2 ols0 0 r/w output level select 0 selects the normal-phase output levels in reset synchronous pwm mode or complementary pwm mode. 0: initial output is high and the active level is low. 1: initial output is low and the active level is high. figure 13.4 shows an example of outputs in reset synchronous pwm mode and complementary pwm mode when ols1 = 0 and ols0 = 0. 1 0 cmd1 cmd0 0 0 r/w r/w combination mode 1 and 0 00: channel 0 and channel 1 operate normally 01: channel 0 and channel 1 are used together to operate in reset synchronous pwm mode 10: channel 0 and channel 1 are used together to operate in complementary pwm mode (transferred at the trough) 11: channel 0 and channel 1 are used together to operate in complementary pwm mode (transferred at the crest) note: when reset synchronous pwm mode or complementary pwm mode is selected by these bits, this setting has the priority to the settings for pwm mode by each bit in tpmr. stop tcnt_0 and tcnt_1 before making settings for reset synchronous pwm mode or complementary pwm mode. section 13 timer z rev. 2.00 sep. 23, 2005 page 184 of 472 rej09b0160-0200 tcnt_0 normal phase counter phase normal phase counter phase active level active level active level active level complementary pwm mode note: write h'00 to tocr to start initial outputs after stopping the counter. reset synchronous pwm mode initial output initial output tcnt_1 figure 13.4 example of outputs in reset synchronous pwm mode and complementary pwm mode section 13 timer z rev. 2.00 sep. 23, 2005 page 185 of 472 rej09b0160-0200 13.3.5 timer output master enable register (toer) toer enables/disables the outputs for channel 0 and channel 1. when wkp4 is selected for inputs, if a low level signal is input to wkp4 , the bits in toer are set to 1 to disable the output for timer z. bit bit name initial value r/w description 7 ed1 1 r/w master enable d1 0: ftiod1 pin output is enabled according to the tpmr, tfcr, and tiorc_1 settings 1: ftiod1 pin output is disabled regardless of the tpmr, tfcr, and tiorc_1 settings (ftiod1 pin is operated as an i/o port). 6 ec1 1 r/w master enable c1 0: ftioc1 pin output is enabled according to the tpmr, tfcr, and tiorc_1 settings 1: ftioc1 pin output is disabled regardless of the tpmr, tfcr, and tiorc_1 settings (ftioc1 pin is operated as an i/o port). 5 eb1 1 r/w master enable b1 0: ftiob1 pin output is enabled according to the tpmr, tfcr, and tiora_1 settings 1: ftiob1 pin output is disabled regardless of the tpmr, tfcr, and tiora_1 settings (ftiob1 pin is operated as an i/o port). 4 ea1 1 r/w master enable a1 0: ftioa1 pin output is enabled according to the tpmr, tfcr, and tiora_1 settings 1: ftioa1 pin output is disabled regardless of the tpmr, tfcr, and tiora_1 settings (ftioa1 pin is operated as an i/o port). 3 ed0 1 r/w master enable d0 0: ftiod0 pin output is enabled according to the tpmr, tfcr, and tiorc_0 settings 1: ftiod0 pin output is disabled regardless of the tpmr, tfcr, and tiorc_0 settings (ftiod0 pin is operated as an i/o port). section 13 timer z rev. 2.00 sep. 23, 2005 page 186 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 ec0 1 r/w master enable c0 0: ftioc0 pin output is enabled according to the tpmr, tfcr, and tiorc_0 settings 1: ftioc0 pin output is disabled regardless of the tpmr, tfcr, and tiorc_0 settings (ftioc0 pin is operated as an i/o port). 1 eb0 1 r/w master enable b0 0: ftiob0 pin output is enabled according to the tpmr, tfcr, and tiora_0 settings 1: ftiob0 pin output is disabled regardless of the tpmr, tfcr, and tiora_0 settings (ftiob0 pin is operated as an i/o port). 0 ea0 1 r/w master enable a0 0: ftioa0 pin output is enabled according to the tpmr, tfcr, and tiora_0 settings 1: ftioa0 pin output is disabled regardless of the tpmr, tfcr, and tiora_0 settings (ftioa0 pin is operated as an i/o port). 13.3.6 timer output co ntrol register (tocr) tocr selects the initial outputs before the first oc currence of a compare ma tch. note that bits ols1 and ols0 in tfcr set these initial outputs in reset synchronous pwm mode and complementary pwm mode. bit bit name initial value r/w description 7 tod1 0 r/w output level select d1 0: 0 output at the ftiod1 pin * 1: 1 output at the ftiod1 pin * 6 toc1 0 r/w output level select c1 0: 0 output at the ftioc1 pin * 1: 1 output at the ftioc1 pin * section 13 timer z rev. 2.00 sep. 23, 2005 page 187 of 472 rej09b0160-0200 bit bit name initial value r/w description 5 tob1 0 r/w output level select b1 0: 0 output at the ftiob1 pin * 1: 1 output at the ftiob1 pin * 4 toa1 0 r/w output level select a1 0: 0 output at the ftioa1 pin * 1: 1 output at the ftioa1 pin * 3 tod0 0 r/w output level select d0 0: 0 output at the ftiod0 pin * 1: 1 output at the ftiod0 pin * 2 toc0 0 r/w output level select c0 0: 0 output at the ftioc0 pin * 1: 1 output at the ftioc0 pin * 1 tob0 0 r/w output level select b0 0: 0 output at the ftiob0 pin * 1: 1 output at the ftiob0 pin * 0 toa0 0 r/w output level select a0 0: 0 output at the ftioa0 pin * 1: 1 output at the ftioa0 pin * note: * the change of the setting is immediatel y reflected in the output value. 13.3.7 timer counter (tcnt) the timer z has two tcnt counters (tcnt_0 and tcnt_1), one for each channel. the tcnt counters are 16-bit readable/writable registers that increment/decrement according to input clocks. input clocks can be selected by bits tpsc2 to tpsc0 in tcr. tcnt0 and tcnt 1 increment/decrement in complementary pwm mode, wh ile they only increment in other modes. the tcnt counters are initialized to h'0000 by compare matches with corresponding gra, grb, grc, or grd, or input captures to gra, grb, grc, or grd (counter clearing function). when the tcnt counters overflow, an ov f flag in tsr for the corresponding channel is set to 1. when tcnt_1 underflows, an udf flag in tsr is set to 1. the tcnt counters cannot be accessed in 8- bit units; they must always be accessed as a 16-bit unit. section 13 timer z rev. 2.00 sep. 23, 2005 page 188 of 472 rej09b0160-0200 13.3.8 general registers a, b, c, and d (gra, grb, grc, and grd) gr are 16-bit registers. timer z has eight genera l registers (gr), four for each channel. the gr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. functions can be switched by tiora and tiorc. the values in gr and tcnt are constantly compared with each ot her when the gr registers are used as output compare register s. when the both values match, the imfa to imfd flags in tsr are set to 1. compare match outputs ca n be selected by tiora and tiorc. when the gr registers are used as input capture re gisters, the tcnt value is stored after detecting external signals. at this point, imfa to imfd flags in the correspond ing tsr are set to 1. detection edges for input capture signals can be selected by tiora and tiorc. when pwm mode, complementary pwm mode, or reset synchronous pwm mode is selected, the values in tiora and tiorc are ignored. upon rese t, the gr registers are set as output compare registers (no output) and initialized to h'ffff. the gr registers ca nnot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. section 13 timer z rev. 2.00 sep. 23, 2005 page 189 of 472 rej09b0160-0200 13.3.9 timer control register (tcr) the tcr registers select a tcnt counter clock, an edge when an external clock is selected, and counter clearing sources. timer z has a total of two tcr registers, one for each channel. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 2 to 0 000: disables tcnt clearing 001: clears tcnt by gra compare match/input capture * 1 010: clears tcnt by grb compare match/input capture * 1 011: synchronization clear; clears tcnt in synchronous with counter clearing of the other channel?s timer * 2 100: disables tcnt clearing 101: clears tcnt by grc compare match/input capture * 1 110: clears tcnt by grd compare match/input capture * 1 111: synchronization clear; clears tcnt in synchronous with counter clearing of the other channel?s timer * 2 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 00: count at rising edge 01: count at falling edge 1x: count at both edges 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 2 to 0 000: internal clock: count by 001: internal clock: count by /2 010: internal clock: count by /4 011: internal clock: count by /8 1xx: external clock: count by ftioa0 (tclk) pin input notes: 1. when gr functions as an output compare register, tcnt is cleared by compare match. when gr functions as input capture, tcnt is cleared by input capture. 2. synchronous operation is set by tmdr. 3. x: don?t care section 13 timer z rev. 2.00 sep. 23, 2005 page 190 of 472 rej09b0160-0200 13.3.10 timer i/o control register (tiora and tiorc) the tior registers control the general registers (gr). timer z has four tior registers (tiora_0, tiora_1, tiorc_0, an d tiorc_1), two for each channe l. in pwm mode including complementary pwm mode and reset synchronous pwm mode, the settings of tior are invalid. ? tiora tiora selects whether gra or grb is used as an output compare register or an input capture register. when an output compare register is sel ected, the output setting is selected. when an input capture register is selected, an input edge of an input capture si gnal is selected. tiora also selects the function of ftioa or ftiob pin. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 iob2 iob1 iob0 0 0 0 r/w r/w r/w i/o control b2 to b0 grb is an output compare register: 000: disables pin output by compare match 001: 0 output by grb compare match 010: 1 output by grb compare match 011: toggle output by grb compare match grb is an input capture register: 100: input capture to grb at the rising edge 101: input capture to grb at the falling edge 11x: input capture to grb at both rising and falling edges 3 ? 1 ? reserved this bit is always read as 1. section 13 timer z rev. 2.00 sep. 23, 2005 page 191 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 1 0 ioa2 ioa1 ioa0 0 0 0 r/w r/w r/w i/o control a2 to a0 gra is an output compare register: 000: disables pin output by compare match 001: 0 output by gra compare match 010: 1 output by gra compare match 011: toggle output by gra compare match gra is an input capture register: 100: input capture to gra at the rising edge 101: input capture to gra at the falling edge 11x: input capture to gra at both rising and falling edges [legend] x: don't care ? tiorc tiorc selects whether grc or grd is used as an output compare register or an input capture register. when an output compare register is selected, the output setting is selected. when an input capture register is selected, an input edge of an input capture si gnal is selected. tiorc also selects the function of ftioc or ftiod pin. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 iod2 iod1 iod0 0 0 0 r/w r/w r/w i/o control d2 to d0 grd is an output compare register: 000: disables pin output by compare match 001: 0 output by grd compare match 010: 1 output by grd compare match 011: toggle output by grd compare match grd is an input capture register: 100: input capture to g rd at the rising edge 101: input capture to grd at the falling edge 11x: input capture to grd at both rising and falling edges section 13 timer z rev. 2.00 sep. 23, 2005 page 192 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 ? 1 ? reserved this bit is always read as 1. 2 1 0 ioc2 ioc1 ioc0 0 0 0 r/w r/w r/w i/o control c2 to c0 grc is an output compare register: 000: disables pin output by compare match 001: 0 output by grc compare match 010: 1 output by grc compare match 011: toggle output by grc compare match grc is an input capture register: 100: input capture to g rc at the rising edge 101: input capture to grc at the falling edge 11x: input capture to grc at both rising and falling edges [legend] x: don't care 13.3.11 timer status register (tsr) tsr indicates generation of an overflow/underflow of tcnt and a compare match/input capture of gra, grb, grc, and grd. these flags are in terrupt sources. if an interrupt is enabled by a corresponding bit in tier, tsr requests an interr upt for the cpu. timer z has two tsr registers, one for each channel. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 udf * 0 r/w underflow flag [setting condition] ? when tcnt_1 underflows [clearing condition] ? when 0 is written to udf after reading udf = 1 section 13 timer z rev. 2.00 sep. 23, 2005 page 193 of 472 rej09b0160-0200 bit bit name initial value r/w description 4 ovf 0 r/w overflow flag [setting condition] ? when the tcnt value underflows [clearing condition] ? when 0 is written to ovf after reading ovf = 1 3 imfd 0 r/w input capt ure/compare match flag d [setting conditions] ? when tcnt = grd and grd is functioning as output compare register ? when tcnt value is transf erred to grd by input capture signal and grd is functioning as input capture register [clearing condition] ? when 0 is written to imfd after reading imfd = 1 2 imfc 0 r/w input capt ure/compare match flag c [setting conditions] ? when tcnt = grc and grc i s functioning as output compare register ? when tcnt value is transf erred to grc by input capture signal and grc is functioning as input capture register [clearing condition] ? when 0 is written to imfc after reading imfc = 1 1 imfb 0 r/w input capt ure/compare match flag b [setting conditions] ? when tcnt = grb and grb is functioning as output compare register ? when tcnt value is transferred to grb by input capture signal and grb is functioning as input capture register [clearing condition] ? when 0 is written to imfb after reading imfb = 1 section 13 timer z rev. 2.00 sep. 23, 2005 page 194 of 472 rej09b0160-0200 bit bit name initial value r/w description 0 imfa 0 r/w input capt ure/compare match flag a [setting conditions] ? when tcnt = gra and gra is functioning as output compare register ? when tcnt value is transferred to gra by input capture signal and gra is functioning as input capture register [clearing condition] ? when 0 is written to imfa after reading imfa = 1 note: bit 5 is not the udf flag in tsr_0. it is a reserved bit. it is always read as 1. 13.3.12 timer interrupt enable register (tier) tier enables or disables interrupt requests for overflow or gr compare match/input capture. timer z has two tier registers, one for each channel. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 ovie 0 r/w overflow interrupt enable 0: interrupt requests (ovi) by ovf or udf flag are disabled 1: interrupt requests (ovi) by ovf or udf flag are enabled 3 imied 0 r/w input capture/com pare match interrupt enable d 0: interrupt requests (imid) by imfd flag are disabled 1: interrupt requests (imid) by imfd flag are enabled 2 imiec 0 r/w input capture/com pare match interrupt enable c 0: interrupt requests (imic) by imfc flag are disabled 1: interrupt requests (imic) by imfc flag are enabled section 13 timer z rev. 2.00 sep. 23, 2005 page 195 of 472 rej09b0160-0200 bit bit name initial value r/w description 1 imieb 0 r/w input capture/com pare match interrupt enable b 0: interrupt requests (imib) by imfb flag are disabled 1: interrupt requests (imib) by imfb flag are enabled 0 imiea 0 r/w input capture/com pare match interrupt enable a 0: interrupt requests (imia) by imfa flag are disabled 1: interrupt requests (imia) by imfa flag are enabled 13.3.13 pwm mode output level control register (pocr) pocr control the active level in pwm mode. ti mer z has two pocr registers, one for each channel. bit bit name initial value r/w description 7 to 3 ? all 1 ? reserved these bits are always read as 1. 2 pold 0 r/w pwm mode output level control d 0: the output level of ftiod is low-active 1: the output level of ftiod is high-active 1 polc 0 r/w pwm mode output level control c 0: the output level of ftioc is low-active 1: the output level of ftioc is high-active 0 polb 0 r/w pwm mode output level control b 0: the output level of ftiob is low-active 1: the output level of ftiob is high-active section 13 timer z rev. 2.00 sep. 23, 2005 page 196 of 472 rej09b0160-0200 13.3.14 interface with cpu 1. 16-bit register tcnt and gr are 16-bit registers. reading/wr iting in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the cpu is 16-bit width. these registers must always be accessed in a 16-bit unit. figu re 13.5 shows an example of accessing the 16-bit registers. h internal data bus bus interface module data bus c p u l tcntl tcnth figure 13.5 accessing opera tion of 16-bit register (between cpu and tcnt (16 bits)) 2. 8-bit register registers other than tcnt and gr are 8-bit regi sters that are connected internally with the cpu in an 8-bit width. figure 13.6 shows an example of accessing the 8-bit registers. tstr h internal data bus bus interface module data bus c p u l figure 13.6 accessing opera tion of 8-bit register (between cpu and tstr (8 bits)) section 13 timer z rev. 2.00 sep. 23, 2005 page 197 of 472 rej09b0160-0200 13.4 operation 13.4.1 counter operation when one of bits str0 and str1 in tstr is set to 1, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. figure 13.7 shows an example of the counter operation setting procedure. [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [2] for periodic counter operation, select the tcnt clearing source with bits cclr2 to cclr0 in tcr. [3] designate the general register selected in [2] as an output compare register by means of tior. [4] set the periodic counter cycle in the general register selected in [2]. [5] set the str bit in tstr to 1 to start the counter operation. operation selection periodic counter free-running counter [1] select counter clock [2] select counter clearing source [3] select output compare register [5] start count operation [4] set period figure 13.7 example of coun ter operation setting procedure section 13 timer z rev. 2.00 sep. 23, 2005 page 198 of 472 rej09b0160-0200 1. free-running count operation and periodic count operation immediately after a reset, the tcnt counters for channels 0 and 1 are all designated as free- running counters. when the relevant bit in tstr is set to 1, the corresponding tcnt counter starts an increment operation as a free-running counter. when tcnt overflows, the ovf flag in tsr is set to 1. if the value of the ovie bit in the corresponding tier is 1 at this point, timer z requests an interrupt. after overflow, tcnt starts an increment operation again from h'0000. figure 13.8 illustrates free-running counter operation. h'ffff tcnt value time h'0000 str0, str1 ovf figure 13.8 free-running counter operation when compare match is selected as the tcnt cl earing source, the tcnt co unter for the relevant channel performs periodic count operation. the gr registers for setting the period are designated as output compare registers, and counter clearing by compare match is sel ected by means of bits cclr1 and cclr0 in tcr. after the settings ha ve been made, tcnt starts an increment operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in gr, the imfa, imfb, imfc, or imfd flag in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding imiea, imieb, imiec, or imied bit in tier is 1 at this point, the timer z requests an interrupt. after a comp are match, tcnt starts an increment operation again from h'0000. figure 13.9 illustrates periodic counter operation. section 13 timer z rev. 2.00 sep. 23, 2005 page 199 of 472 rej09b0160-0200 h'0000 time counter cleared by gr compare match str gr value tcnt value imf figure 13.9 periodic counter operation 2. tcnt count timing a. internal clock operation a system clock ( ) or three types of clocks ( /2, /4, or /8) that divides the system clock can be selected by bits tpsc2 to tpsc0 in tcr. figure 13.10 illustrates this timing. tcnt tcnt input internal clock n-1 n n+1 figure 13.10 count timing at internal clock operation section 13 timer z rev. 2.00 sep. 23, 2005 page 200 of 472 rej09b0160-0200 b. external clock operation an external clock input pin (tclk) can be se lected by bits tpsc2 to tpsc0 in tcr, and a detection edge can be selected by bits ckeg 1 and ckeg0. to detect an external clock, the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock needs two or more system clocks. note that an external clock does not operate correctly with the lower pulse width. figure 13.11 illustrates the detection timing of the rising and falling edges. tcnt external clock input pin tcnt input n-1 n n+1 figure 13.11 count timing at external clock operation (both edges detected) section 13 timer z rev. 2.00 sep. 23, 2005 page 201 of 472 rej09b0160-0200 13.4.2 waveform output by compare match timer z can perform 0, 1, or toggle output from the corresponding ftioa, ftiob, ftioc, or ftiod output pin using compare match a, b, c, or d. figure 13.12 shows an example of the setting procedure for waveform output by compare match. [1] select 0 output, 1 output, or toggle output as a compare much output, by means of tior. the initial values set in tocr are output unit the first compare match occurs. [2] set the timing for compare match generation in gra/grb/grc/grd. [3] enable or disable the timer output by toer. [4] set the str bit in tstr to 1 to start the tcnt count operation. [1] output selection select waveform output mode [2] set output timing [3] enable waveform output [4] start count operation section 13 timer z rev. 2.00 sep. 23, 2005 page 202 of 472 rej09b0160-0200 1. examples of waveform output operation figure 13.13 shows an example of 0 output/1 output. in this example, tcnt has been designated as a free-running counter, and settings have been made such that 0 is output by compare match a, and 1 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. h'ffff h'0000 ftiob time no change no change no change no change tcnt value ftioa figure 13.13 example of 0 output/1 output operation figure 13.14 shows an example of toggle output. in this example, tcnt has b een designated as a periodic co unter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b. section 13 timer z rev. 2.00 sep. 23, 2005 page 203 of 472 rej09b0160-0200 grb gra h'0000 ftiob toggle output toggle output time tcnt value ftioa figure 13.14 example of toggle output operation 2. output compare timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next tcnt input clock pulse is input. figure 13.15 shows an example of the output compare timing. section 13 timer z rev. 2.00 sep. 23, 2005 page 204 of 472 rej09b0160-0200 tcnt ftioa to ftiod compare match signal tcnt input gr n n n+1 figure 13.15 out put compare timing 13.4.3 input ca pture function the tcnt value can be transferred to gr on detection of the input edge of the input capture/output compare pin (ftioa, ftiob, ftioc, or ftiod). rising edge, falling edge, or both edges can be selected as the detected edge. when the input capture fu nction is used, the pulse width or period can be measured. figure 13.16 shows an example of the i nput capture operati on setting procedure. section 13 timer z rev. 2.00 sep. 23, 2005 page 205 of 472 rej09b0160-0200 [1] designate gr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. [2] set the str bit in tstr to 1 to start the tcnt counter operation. [1] input selection select input edge of input capture [2] start counter operation figure 13.16 example of input ca pture operation setting procedure 1. example of input capture operation figure 13.17 shows an example of input capture operation. in this example, both rising and falling edges have been selected as the ftioa pin input capture input edge, the falling edge has been se lected as the ftiob pin input capture input edge, and counter clearing by grb input capture has been designated for tcnt. section 13 timer z rev. 2.00 sep. 23, 2005 page 206 of 472 rej09b0160-0200 ftioa tcnt value counter cleared by ftiob input (rising edge) time ftiob gra h'0005 h'0005 h'0000 h'0160 h'0160 grb h'0180 h'0180 figure 13.17 example of input capture operation 2. input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior. figure 13.18 shows the timing when the risi ng edge is selected. the pulse width of the input capture signal must be at least two system clock ( ) cycles. section 13 timer z rev. 2.00 sep. 23, 2005 page 207 of 472 rej09b0160-0200 tcnt input capture signal input capture input gr n n figure 13.18 input capture signal timing 13.4.4 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables gr to be increased w ith respect to a single time base. figure 13.19 shows an example of the synchronous operation setting procedure. section 13 timer z rev. 2.00 sep. 23, 2005 page 208 of 472 rej09b0160-0200 no yes synchronous operation selection clearing source generation channel? set synchronous operation select counter clearing source synchronous presetting set tcnt synchronous clearing [1] [2] [3] select counter clearing source [4] start counter operation [5] start counter operation [5] [1] set the sync bits in tmdr to 1. [2] when a value is written to either of the tcnt counters, the same value is simultaneously written to the other tcnt counter. [3] set bits cclr1 and cclr0 in tcr to specify counter clearing by compare match/input capture. [4] set bits cclr1 and cclr0 in tcr to designate synchronous clearing for the counter clearing source. [5] set the str bit in tstr to 1 to start the count operation. section 13 timer z rev. 2.00 sep. 23, 2005 page 209 of 472 rej09b0160-0200 gra_0 time synchronous clearing by gra_0 compare match tcnt values gra_1 grb_0 grb_1 h'0000 ftiob0 ftiob1 figure 13.20 example of synchronous operation 13.4.5 pwm mode in pwm mode, pwm waveforms are output from the ftiob, ftioc, and ftiod output pins with gra as a cycle register and grb, grc, and grd as duty registers. the initial output level of the corresponding pin depends on the setting values of tocr and pocr. table 13.3 shows an example of the initial output level of the ftiob0 pin. the output level is determined by the polb to pold bits corresponding to pocr. when polb is 0, the ftiob output pin is set to 0 by compare match b and set to 1 by compare match a. when polb is 1, the ftiob output pin is set to 1 by compare match b and cleared to 0 by compare match a. in pwm mode, maximum 6-phase pwm outputs are possible. figure 13.21 shows an example of the pwm mode setting procedure. section 13 timer z rev. 2.00 sep. 23, 2005 page 210 of 472 rej09b0160-0200 table 13.3 initial output level of ftiob0 pin tob0 polb initial output level 0 0 1 0 1 0 1 0 0 1 1 1 [1] select the counter clock with bits tpsc2 to tosc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr1 and cclr0 in tcr to select the counter clearing source. [3] select the pwm mode with bits pwmb0 to pwmd0 and pwmb1 to pwmd1 in tpmr. [4] set the initial output value with bits tob0 to tod0 and tob1 to tod1 in tocr. [5] set the output level with bits polb to pold in pocr. [6] set the cycle in gra, and set the duty in the other gr. [7] enable or disable the timer output by toer. [8] set the str bit in tstr to 1 and start the counter operation. [1] [2] [3] [4] [5] [6] [7] pwm mode select counter clock select counter clearing source set pwm mode set initial output level select output level set gr enable waveform output [8] start counter operation section 13 timer z rev. 2.00 sep. 23, 2005 page 211 of 472 rej09b0160-0200 figure 13.22 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is reset at compare match a, and the output signa ls go to 0 at compare match b, c, and d (tob, toc, and tod = 0, polb, polc, and pold = 0). gra tcnt value time counter cleared by gra compare match grb grc grd h'0000 ftioc ftiod ftiob figure 13.22 example of pwm mode operation (1) figure 13.23 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is reset at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0, polb, polc, and pold = 1). section 13 timer z rev. 2.00 sep. 23, 2005 page 212 of 472 rej09b0160-0200 gra grb grc grd h'0000 ftioc ftiod ftiob counter cleared by gra compare match time tcnt value figure 13.23 example of pwm mode operation (2) figures 13.24 (when tob, toc, and tod = 0, polb, polc, and pold = 0) and 13.25 (when tob, toc, and tod = 0, polb, polc, and pold = 1) show examples of the output of pwm waveforms with duty cycles of 0% and 100% in pwm mode. section 13 timer z rev. 2.00 sep. 23, 2005 page 213 of 472 rej09b0160-0200 gra tcnt value 0% duty 0% duty time time time grb rewritten tcnt value grb rewritten grb rewritten grb rewritten tcnt value grb rewritten grb rewritten grb rewritten when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. grb rewritten 100% duty 100% duty grb h'0000 ftiob gra grb h'0000 ftiob gra grb h'0000 ftiob figure 13.24 example of pwm mode operation (3) section 13 timer z rev. 2.00 sep. 23, 2005 page 214 of 472 rej09b0160-0200 gra grb h'0000 ftiob gra grb h'0000 ftiob gra grb h'0000 ftiob tcnt value 0% duty time grb rewritten grb rewritten time tcnt value grb rewritten grb rewritten grb rewritten 100% duty 0% duty time tcnt value grb rewritten grb rewritten grb rewritten 100% duty when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. figure 13.25 example of pwm mode operation (4) section 13 timer z rev. 2.00 sep. 23, 2005 page 215 of 472 rej09b0160-0200 13.4.6 reset synchronous pwm mode three normal- and counter-phase pwm waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. in reset synchronous pwm mode, the ftiob0 to ftiod0 and ftioa1 to ftiod1 pins become pwm-output pins automatically. tcnt_0 performs an increment operation. tables 13.4 and 13.5 show the pwm-output pins used and the register settings, respectively. figure 13.26 shows the example of reset synchronous pwm mode setting procedure. table 13.4 output pins in reset synchronous pwm mode channel pin name input/output pin function 0 ftioc0 output toggle output in synchronous with pwm cycle 0 ftiob0 output pwm output 1 0 ftiod0 output pwm output 1 (counter-phase waveform of pwm output 1) 1 ftioa1 output pwm output 2 1 ftioc1 output pwm output 2 (counter-phase waveform of pwm output 2) 1 ftiob1 output pwm output 3 1 ftiod1 output pwm output 3 (counter-phase waveform of pwm output 3) table 13.5 register settings in reset synchronous pwm mode register description tcnt_0 initial setting of h'0000 tcnt_1 not used (independently operates) gra_0 sets counter cycle of tcnt_0 grb_0 set a changing point of the pwm waveform output from pins ftiob0 and ftiod0. gra_1 set a changing point of the pwm waveform output from pins ftioa1 and ftioc1. grb_1 set a changing point of the pwm waveform output from pins ftiob1 and ftiod1. section 13 timer z rev. 2.00 sep. 23, 2005 page 216 of 472 rej09b0160-0200 [1] clear bit str0 in tstr to 0 and stop the counter operation of tcnt_0. set reset synchronous pwm mode after tcnt_0 stops. [2] select the counter clock with bits tpsc2 to tosc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [3] use bits cclr1 and cclr0 in tcr to select counter clearing source gra_0. [4] select the reset synchronous pwm mode with bits cmd1 and cmd0 in tfcr. ftiob0 to ftiod0 and ftioa1 to ftiod1 become pwm output pins automatically. [5] set h'00 to tocr. [6] set tcnt_0 as h'0000. tcnt1 does not need to be set. [7] gra_0 is a cycle register. set a cycle for gra_0. set the changing point timing of the pwm output waveform for grb_0, gra_1, and grb_1. [8] enable or disable the timer output by toer. [9] set the str bit in tstr to 1 and start the counter operation. [1] reset synchronous pwm mode [2] stop counter operation [3] select counter clock [4] select counter clearing source [5] set reset synchronous pwm mode [6] initialize the output pin [7] set tcnt [8] set gr [9] start counter operation enable waveform output section 13 timer z rev. 2.00 sep. 23, 2005 page 217 of 472 rej09b0160-0200 figures 13.27 and 13.28 show examples of operation in reset synchronous pwm mode. gra_0 tcnt value counter cleared by gra compare match time grb_0 gra_1 grb_1 h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 figure 13.27 example of reset synchronous pwm mode operation (ols0 = ols1 = 1) section 13 timer z rev. 2.00 sep. 23, 2005 page 218 of 472 rej09b0160-0200 gra_0 grb_0 gra_1 grb_1 h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 tcnt value counter cleared by gra compare match time figure 13.28 example of reset synchronous pwm mode operation (ols0 = ols1 = 0) in reset synchronous pwm mode, tcnt_0 and tcnt_1 perform increment and independent operations, respectively. however, gra_1 and grb_1 are separated from tcnt_1. when a compare match occurs between tcnt_0 and gra_ 0, a counter is cleared and an increment operation is restarted from h'0000. the pwm pin outputs 0 or 1 whenever a compare match between grb_0, gra_1, grb_1 and tcnt_0 or counter clearing occur. for details on operations when reset synchronous pwm mode and buffer operation are simultaneously set, refer to section 13.4.8, buffer operation. section 13 timer z rev. 2.00 sep. 23, 2005 page 219 of 472 rej09b0160-0200 13.4.7 complementary pwm mode three pwm waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. in complementary pwm mode, the ftiob0 to ftiod0 and ftioa1 to ftiod1 pins become pwm-output pins automatically. tcnt_0 and tcnt_1 perform an increment or decrement operation. tables 13.6 and 13.7 show the output pins and register settings in complementary pwm mode, respectively. figure 13.29 shows the example of complementary pwm mode setting procedure. table 13.6 output pins in complementary pwm mode channel pin name input/output pin function 0 ftioc0 output toggle output in synchronous with pwm cycle 0 ftiob0 output pwm output 1 0 ftiod0 output pwm output 1 (counter-phase waveform non- overlapped with pwm output 1) 1 ftioa1 output pwm output 2 1 ftioc1 output pwm output 2 (counter-phase waveform non- overlapped with pwm output 2) 1 ftiob1 output pwm output 3 1 ftiod1 output pwm output 3 (counter-phase waveform non- overlapped with pwm output 3) table 13.7 register settings in complementary pwm mode register description tcnt_0 initial setting of non-overlapped periods (non-overlapped periods are differences with tcnt_1) tcnt_1 initial setting of h'0000 gra_0 sets (upper limit value ? 1) of tcnt_0 grb_0 set a changing point of the pwm waveform output from pins ftiob0 and ftiod0. gra_1 set a changing point of the pwm waveform output from pins ftioa1 and ftioc1. grb_1 set a changing point of the pwm waveform output from pins ftiob1 and ftiod1. section 13 timer z rev. 2.00 sep. 23, 2005 page 220 of 472 rej09b0160-0200 [1] clear bits str0 and str1 in tstr to 0, and stop the counter operation of tcnt_0. stop tcnt_0 and tcnt_1 and set complementary pwm mode. [2] write h'00 to tocr. [3] use bits tpsc2 to tpsc0 in tcr to select the same counter clock for channels 0 and 1. when an external clock is selected, select the edge of the external clock by bits ckeg1 and ckeg0 in tcr. do not use bits cclr1 and cclr0 in tcr to clear the counter. [4] use bits cmd1 and cmd0 in tfcr to set complementary pwm mode. ftiob0 to ftiod0 and ftioa1 to ftiod1 automatically become pwm output pins. [5] set h'00 to tocr. [6] tcnt_1 must be h'0000. set a non- overlapped period to tcnt_0. [7] gra_0 is a cycle register. set the cycle to gra_0. set the timing to change the pwm output waveform to grb_0, gra_1, and grb_1. note that the timing must be set within the range of compare match carried out for tcnt_0 and tcnt_1. for gr settings, see 3. setting gr value in complementary pwm mode in section 13.4.7. [8] use toer to enable or disable the timer output. [9] set the str0 and str1 bits in tstr to 1 to start the count operation. [1] complementary pwm mode stop counter operation note: to re-enter complementary pwm mode, first, enter a mode other than the complementary pwm mode. after that, repeat the setting procedures from step [1]. for settings of waveform outputs with a duty cycle of 0% and 100%, see the settings shown in 2. examples of complementary pwm mode operation and 3. setting gr value in complementary pwm mode in section 13.4.7. [2] initialize output pin [3] select counter clock [4] set complementary pwm mode [5] initialize output pin section 13 timer z rev. 2.00 sep. 23, 2005 page 221 of 472 rej09b0160-0200 1. canceling procedure of complementary pwm mode: figure 13.30 shows the complementary pwm mode canceling procedure. [1] clear bit cmd1 in tfcr to 0, and set channels 0 and 1 to normal operation. [2] after setting channels 0 and 1 to normal operation, clear bits str0 and str1 in tstr to 0 and stop tcnt0 and tcnt1. [1] [2] complementary pwm mode stop counter operation cancel complementary pwm mode section 13 timer z rev. 2.00 sep. 23, 2005 page 222 of 472 rej09b0160-0200 gra_0 grb_0 gra_1 grb_1 tcnt values tcnt_0 and gra_0 are compared and their contents match time h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 figure 13.31 example of complementary pwm mode operation (1) section 13 timer z rev. 2.00 sep. 23, 2005 page 223 of 472 rej09b0160-0200 figure 13.32 (1) and (2) show examples of pwm waveform output with 0% duty and 100% duty in complementary pwm mode (for one phase). ? tpsc2 = tpsc1 = tpsc0 = 0 set grb_0 to h'0000 or a value equal to or more than gra_0. the waveform with a duty cycle of 0% and 100% can be output. when buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. for details on buffer operation, refer to section 13.4.8, buffer operation. ? other than tpsc2 = tpsc1 = tpsc0 = 0 set grb_0 to satisfy the following expression: gra_0 + 1 < grb_0 < h'ffff. the waveform with a duty cycle of 0% and 100% can be output. for details on 0%- and 100%-duty cycle waveform output, see 3. c., outputting a waveform with a duty cycle of 0% and 100% in section 13.4.7. section 13 timer z rev. 2.00 sep. 23, 2005 page 224 of 472 rej09b0160-0200 gra0 h'0000 ftiob0 ftiod0 gra0 (b) when duty is 100% 100% duty tcnt values tcnt values time time 0% duty (a) when duty is 0% grb0 h'0000 ftiob0 ftiod0 grb0 figure 13.32 (1) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 = 0) (2) section 13 timer z rev. 2.00 sep. 23, 2005 page 225 of 472 rej09b0160-0200 gra0 h'0000 ftiob0 ftiod0 gra0 (b) when duty is 100% 100% duty tcnt values tcnt values time time 0% duty (a) when duty is 0% grb0 h'0000 ftiob0 ftiod0 grb0 figure 13.32 (2) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 0) (3) section 13 timer z rev. 2.00 sep. 23, 2005 page 226 of 472 rej09b0160-0200 in complementary pwm mode, when the counter switches from up-counter to down-counter or vice versa, tcnt_0 and tcnt_1 overshoots or undershoots, respectivel y. in this case, the conditions to set the imfa flag in channel 0 and the udf flag in channel 1 differ from usual settings. also, the transfer conditio ns in buffer operation differ from usual settings. such timings are shown in figures 13.33 and 13.34. gr buffer transfer signal set to 1 flag is not set transferred to buffer not transferred to buffer n+1 gra_0 tcnt n n-1 n-1 n n imfa figure 13.33 timing of overshooting h'ffff h'0001 h'0001 h'0000 h'0000 gr udf tcnt buffer transfer signal set to 1 flag is not set transferred to buffer not transferred to buffer figure 13.34 timing of undershooting section 13 timer z rev. 2.00 sep. 23, 2005 page 227 of 472 rej09b0160-0200 when the counter is incremented or decremented, th e imfa flag of channel 0 is set to 1, and when the register is underflowed, the udf flag of channel 0 is set to 1. after buffer operation has been designated for br, br is transfer red to gr when the counter is incremented by compare match a0 or when tcnt_1 is underflowed. if the or /2 clock is selected by tpsc2 to tpsc0 bits, the ovf flag is not set to 1 at the timing that the counter value changes from h'ffff to h'0000. if the /4 or /8 clock is selected by tpsc2 to tpsc0 bits, the ovf flag is set to 1. 3. setting gr value in complementary pwm mode: to set the general register (gr) or modify gr during operation in complementary pwm mode, refer to the following notes. a. initial value a. when other than tpsc2 = tpsc1 = tpsc0 = 0, the gra_0 value must be equal to h'fffc or less. when tpsc2 = tpsc1 = tpsc0 = 0, the gra_0 value can be set to h'ffff or less. b. h'0000 to t ? 1 (t: initial value of tcnt0) must not be set for the initial value. c. gra_0 ? (t ? 1) or more must not be set for the initial value. d. when using buffer operation, the same values must be set in the buffer registers and corresponding general registers. b. modifying the setting value a. writing to gr directly must be performed while the tcnt_1 and tcnt_0 values should satisfy the following expression: h'0000 tcnt_1 < previous gr value, and previous gr value < tcnt_0 gra_0. otherwise, a waveform is not output correctly. for details on outputting a waveform with a duty cycle of 0% and 100%, see c., outputting a waveform with a duty cycle of 0% and 100%. b. do not write the following values to gr directly. when writing the values, a waveform is not output correctly. h'0000 gr t ? 1 and gra_0 ? (t ? 1) gr < gra_0 when tpsc2 = tpsc1 = tpsc0 = 0 h'0000 < gr t ? 1 and gra_0 ? (t ? 1) gr < gra_0 + 1 when tpsc2 = tpsc1 = tpsc0 = 0 c. do not change settings of gra_0 during operation. c. outputting a waveform with a duty cycle of 0% and 100% a. buffer operation is not used and tpsc2 = tpsc1 = tpsc0 = 0 write h'0000 or a value equal to or more th an the gra_0 value to gr directly at the timing shown below. ? to output a 0%-duty cycle waveform, write a value equal to or more than the gra_0 value while h'0000 tcnt_1 < previous gr value ? to output a 100%-duty cycle waveform, write h'0000 while previous gr value< tcnt_0 gra_0 section 13 timer z rev. 2.00 sep. 23, 2005 page 228 of 472 rej09b0160-0200 to change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure. ? to change duty cycles while a 0%-duty cycle waveform is being output, write to gr while h'0000 tcnt_1 < previous gr value ? to change duty cycles while a 100%-duty cycle waveform is being output, write to gr while previous gr value< tcnt_0 gra_0 note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. b. buffer operation is used and tpsc2 = tpsc1 = tpsc0 = 0 write h'0000 or a value equal to or more than the gra_0 value to the buffer register. ? to output a 0%-duty cycle waveform, write a value equal to or more than the gra_0 value to the buffer register ? to output a 100%-duty cycle waveform, write h'0000 to the buffer register for details on buffer operation, see section 13.4.8, bu ffer operation. c. buffer operation is not used and other than tpsc2 = tpsc1 = tpsc0 = 0 write a value which satisfies gra_0 + 1 < gr < h'ffff to gr directly at the timing shown below. ? to output a 0%-duty cycle wavefo rm, write the value while h'0000 tcnt_1 < previous gr value ? to output a 100%-duty cycle waveform, write the value while previous gr value< tcnt_0 gra_0 to change duty cycles while a waveform with a duty cycle of 0% and 100% is being output, the following procedure must be followed. ? to change duty cycles while a 0%-duty cycle waveform is being output, write to gr while h'0000 tcnt_1 < previous gr value ? to change duty cycles while a 100%-duty cycle waveform is being output, write to gr while previous gr value< tcnt_0 gra_0 note that changing from a 0%-duty cycle waveform to a 100%-duty cycle waveform and vice versa is not possible. d. buffer operation is used and other than tpsc2 = tpsc1 = tpsc0 = 0 write a value which satisfies gra_0 + 1 < gr < h'ffff to the buffer register. a waveform with a duty cycle of 0% can be output. however, a waveform with a duty cycle of 100% cannot be output using the buffer operation. also, the buffer operation cannot be used to change duty cycles while a waveform wi th a duty cycle of 100% is being output. for details on buffer operation, see section 13.4.8, buffer operation. section 13 timer z rev. 2.00 sep. 23, 2005 page 229 of 472 rej09b0160-0200 13.4.8 buffer operation buffer operation differs depending on whether gr has been designated for an input capture register or an output compare register, or in reset synchronous pwm mode or complementary pwm mode. table 13.8 shows the register combin ations used in buffer operation. table 13.8 register combinat ions in buffer operation general register buffer register gra grc grb grd 1. when gr is an output compare register when a compare match occurs, the value in the bu ffer register of the corresponding channel is transferred to the general register. this operation is illustrated in figure 13.35. buffer register comparator tcnt general register compare match signal figure 13.35 compare match buffer operation 2. when gr is an input capture register when an input capture occurs, the value in tcnt is transferred to the general register and the value previously stored in the general register is transferred to the buffer register. this operation is illustrated in figure 13.36. section 13 timer z rev. 2.00 sep. 23, 2005 page 230 of 472 rej09b0160-0200 tcnt buffer register general register input capture signal figure 13.36 input capture buffer operation 3. complementary pwm mode when the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general regi ster. here, the value of the buffer register is transferred to the general register in the following timing: a. when tcnt_0 and gra_0 are co mpared and their contents match b. when tcnt_1 underflows 4. reset synchronous pwm mode the value of the buffer register is transferred from compare match a0 to the general register. 5. example of buffer operation setting procedure figure 13.37 shows an example of the buffer operation setting procedure. [1] designate gr as an input capture register or output compare register by means of tior. [2] designate gr for buffer operation with bits bfd1, bfc1, bfd0, or bfc0 in tmdr. [3] set the str bit in tstr to 1 to start the count operation of tcnt. [1] [2] [3] select gr function set buffer operation start count operation buffer operation section 13 timer z rev. 2.00 sep. 23, 2005 page 231 of 472 rej09b0160-0200 6. examples of buffer operation figure 13.38 shows an operation example in which gra has been designated as an output compare register, and buffer operation has been designated for gra and grc. this is an example of tcnt operating as a periodic counter cleared by compare match b. pins ftioa and ftiob are set for toggle output by compare match a and b. as buffer operation has been set, when compare match a occurs, the ftioa pin performs toggle outputs and the value in buffer register is simultaneously transferred to the general register. this operation is repeated each time that compare match a occurs. the timing to transfer data is shown in figure 13.39. grb tcnt value counter is cleared by gbr compare match time compare match a h'0250 h'0200 h'0100 h'0000 ftiob ftioa h'0200 h'0250 h'0200 h'0200 h'0100 h'0200 grc h'0100 gra figure 13.38 example of buffer operation (1) (buffer operation for ou tput compare register) section 13 timer z rev. 2.00 sep. 23, 2005 page 232 of 472 rej09b0160-0200 gra n n tcnt compare match signal buffer transfer signal n n+1 grc n figure 13.39 example of compare match timing for buffer operation figure 13.40 shows an operation example in which gra has been designated as an input capture register, and buffer operation has be en designated for gra and grc. counter clearing by input capture b has been set for tcnt, and falling edges have been selected as the fiocb pin input capture input edge. and both rising and falling edges have been selected as the fioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in gra upon the occurrence of input capture a, the value previo usly stored in gra is simultaneously transferred to grc. the transfer timing is shown in figure 13.41. section 13 timer z rev. 2.00 sep. 23, 2005 page 233 of 472 rej09b0160-0200 h'0180 h'0160 h'0005 h'0000 ftiob ftioa h'0160 h'0005 h'0005 gra h'0160 grc h'0180 grb tcnt value counter is cleared by the input capture b time input capture a figure 13.40 example of buffer operation (2) (buffer operation for i nput capture register) section 13 timer z rev. 2.00 sep. 23, 2005 page 234 of 472 rej09b0160-0200 tcnt ftio pin input capture signal nnn+1 n+1 gra m n n n grc m m n m figure 13.41 input capture timing of buffer operation figures 13.42 and 13.43 show the operation examples when buffer operation has been designated for grb_0 and grd_0 in complementary pw m mode. these are examples when a pwm waveform of 0% duty is created by using the buffer operation and performing grd_0 gra_0. data is transferred from grd_0 to grb_0 according to the settings of cmd_0 and cmd_1 when tcnt_0 and gra_0 are compared and their contents match or when tcnt_1 underflows. however, when grd_0 gra_0, data is transferred from grd_0 to grb_0 when tcnt_1 underflows regardless of the setting of cmd_0 and cmd_1. when grd_0 = h'0000, data is transferred from grd_0 to grb_0 when tcnt_0 and gra_0 are compared and their contents match regardless of the settings of cmd_0 and cmd_1. section 13 timer z rev. 2.00 sep. 23, 2005 page 235 of 472 rej09b0160-0200 gra_0 h'0000 h'0999 ftiob0 ftiod0 tcnt_0 tcnt values time grb_0 (when restored, data will be transferred to the saved location regardless of the cmd1 and cmd0 values) tcnt_1 h'0999 h'0999 h'0999 h'0999 h'1fff h'0999 grd_0 h'1fff grb_0 figure 13.42 buffer operation (3) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1) section 13 timer z rev. 2.00 sep. 23, 2005 page 236 of 472 rej09b0160-0200 gra_0 h'0000 h'0999 ftioc0 ftiod0 tcnt values grb_0 (when restored, data will be transferred to the saved location regardless of the cmd1 and cmd0 values) time tcnt_0 tcnt_1 grb_0 h'0999 h'0999 h'0999 h'0000 h'0999 h'0000 grd_0 grb_0 figure 13.43 buffer operation (4) (buffer operation in complementar y pwm mode cmd1 = cmd0 = 1) 13.4.9 timer z output timing the outputs of channels 0 and 1 can be disabled or inverted by the settings of toer and tocr and the external level. 1. output disable/enable timing of timer z by toer: setting the master enable bit in toer to 1 disables the output of timer z. by setting the pcr and pdr of the corresponding i/o port beforehand, any value can be output. figure 13.44 shows the timing to enable or disable the output of timer z by toer. section 13 timer z rev. 2.00 sep. 23, 2005 page 237 of 472 rej09b0160-0200 t 1 t 2 toer address bus toer address timer z output pin timer z output i/o port i/o port timer output figure 13.44 example of ou tput disable timing of timer z by writing to toer 2. output disable timing of timer z by external trigger: when p54/ wkp4 is set as a wkp4 input pin, and low level is input to wkp4 , the master enable bit in toer is set to 1 and the output of timer z will be disabled. wkp4 toer timer z output pin timer z output i/o port timer z output i/o port n h'ff figure 13.45 example of output disable timing of timer z by external trigger section 13 timer z rev. 2.00 sep. 23, 2005 page 238 of 472 rej09b0160-0200 3. output inverse timing by tfcr: the output level can be inverted by inverting the ols1 and ols0 bits in tfcr in reset synchronous pwm mode or complementary pwm mode. figure 13.46 shows the timing. t 1 t 2 tfcr inverted timer z output pin address bus toer address figure 13.46 example of ou tput inverse timing of ti mer z by writing to tfcr 4. output inverse timing by pocr: the output level can be inverted by inverting the pold, polc, and polb bits in pocr in pwm mode. figure 13.47 shows the timing. t 1 t 2 tfcr address bus pocr address timer z output pin inverted figure 13.47 example of output inverse timing of timer z by writing to pocr section 13 timer z rev. 2.00 sep. 23, 2005 page 239 of 472 rej09b0160-0200 13.5 interrupts there are three kinds of timer z interrupt sources; input capture/compare match, overflow, and underflow. an interrupt is requested when the corresp onding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 13.5.1 status fl ag set timing 1. imf flag set timing: the imf flag is set to 1 by the compare match signal that is generated when the gr matches with the tc nt. the compare match signal is generated at the last state of matching (timing to update the counter value when the gr and tcnt match). therefore, when the tcnt and gr matches, the compare match signal will not be generated until the tcnt input clock is generated. figure 13.48 shows the timing to set the imf flag. imf itmz tcnt tcnt input clock compare match signal n n+1 gr n figure 13.48 imf flag set timi ng when compare match occurs section 13 timer z rev. 2.00 sep. 23, 2005 page 240 of 472 rej09b0160-0200 2. imf flag set timing at input capture: when an input capture signal is generated, the imf flag is set to 1 and the value of tcnt is simultane ously transferred to corresponding gr. figure 13.49 shows the timing. imf input capture signal tcnt n gr n itmz figure 13.49 imf flag set timing at input capture 3. overflow flag (ovf) set timing: the overflow flag is set to 1 when the tcnt overflows. figure 13.50 shows the timing. ovf tcnt overflow signal h'0000 h'ffff itmz figure 13.50 ovf flag set timing section 13 timer z rev. 2.00 sep. 23, 2005 page 241 of 472 rej09b0160-0200 13.5.2 status flag clearing timing the status flag can be cleared by writing 0 after reading 1 from the cpu. figure 13.51 shows the timing in this case. address tsr address wtsr (internal write signal) imf, ovf itmz figure 13.51 status flag clearing timing section 13 timer z rev. 2.00 sep. 23, 2005 page 242 of 472 rej09b0160-0200 13.6 usage notes 1. contention between tcnt write and clear opera tions: if a counter clear signal is generated in the t 2 state of a tcnt write cycle, tcnt clearin g has priority and the tcnt write is not performed. figure 13.52 shows the timing in this case. t 1 t 2 tcnt tcnt write cycle tcnt address wtcnt (internal write signal) clearing has priority. counter clear signal n h'0000 figure 13.52 contention betwee n tcnt write and clear operations section 13 timer z rev. 2.00 sep. 23, 2005 page 243 of 472 rej09b0160-0200 2. contention between tcnt write and incremen t operations: if increm entation is done in t 2 state of a tcnt write cycle, tcnt writing has priority. figure 13.53 shows the timing in this case. t 1 t 2 tcnt tcnt write cycle tcnt address wtcnt (internal write signal) tcnt input clock tcnt write data n m figure 13.53 contention between tc nt write and increment operations section 13 timer z rev. 2.00 sep. 23, 2005 page 244 of 472 rej09b0160-0200 3. contention between gr write and compare matc h: if a compare match occurs in the t 2 state of a gr write cycle, gr write has priority and the compare match signal is disabled. figure 13.54 shows the timing in this case. t 1 t 2 gr n m tcnt gr write cycle gr address wgr (internal write signal) gr write data compare match signal disabled n n+1 figure 13.54 contention between gr write and compare match section 13 timer z rev. 2.00 sep. 23, 2005 page 245 of 472 rej09b0160-0200 4. contention between tcnt write and overflow/underflow: if overflow/underflow occurs in the t 2 state of a tcnt write cycle, tcnt write ha s priority without an increment operation. at this time, the ovf flag is set to 1. figure 13.55 shows the timing in this case. t 1 t 2 tcnt h'ffff m ovf tcnt address wtcnt (internal write signal) tcnt input clock overflow signal tcnt write data tcnt write cycle figure 13.55 contention be tween tcnt write and overflow section 13 timer z rev. 2.00 sep. 23, 2005 page 246 of 472 rej09b0160-0200 5. contention between gr read and input capture: if an input capture signal is generated in the t 1 state of a gr read cycle, the data that is read will be transferre d before input capture transfer. figure 13.56 shows the timing in this case. t 1 t 2 gr gr read cycle gr address internal read signal input capture signal internal data bus x x m figure 13.56 contention between gr read and input capture section 13 timer z rev. 2.00 sep. 23, 2005 page 247 of 472 rej09b0160-0200 6. contention between count clearing and incremen t operations by input capture: if an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. the tcnt contents before clearing counter are transferred to gr. figu re 13.57 shows the timing in this case. tcnt input capture signal counter clear signal tcnt input clock clearing has priority. n h'0000 gr n figure 13.57 contention between co unt clearing and increment operations by input capture section 13 timer z rev. 2.00 sep. 23, 2005 page 248 of 472 rej09b0160-0200 7. contention between gr write and input capture: if an input capture signal is generated in the t 2 state of a gr write cycle, the input capture op eration has priority and the write to gr is not performed. figure 13.58 shows the timing in this case. t 1 t 2 tcnt n gr write cycle gr address input capture signal wgr (internal write signal) address bus gr write data gr m figure 13.58 contention between gr write and input capture 8. notes on setting reset synchronous pwm mode/complementary pwm mode: when bits cmd1 and cmd0 in tfcr are set, note the following: a. write bits cmd1 and cmd0 while tcnt_1 and tcnt_0 are halted. b. changing the settings of reset synchronous pwm mode to complementary pwm mode or vice versa is disabled. set reset synchronous pwm mode or complementary pwm mode after the normal operation (bits cmd1 and cm d0 are cleared to 0) has been set. 9. note on clearing tsr flag: when a specific flag in tsr is cleared, a combination of the bclr or mov instructions is used to read 1 from the flag and then write 0 to the flag. however, if another bit is set during this processing, the bit may also be cleared simultaneously. to avoid this, the following processing that does not use the bclr instruction must be executed. note that this not e is only applied to the f-ztat version. this problem has already been solved in the mask rom version. example: when clearing bit 4 (ovf) in tsr mov.b @tsr,r0l section 13 timer z rev. 2.00 sep. 23, 2005 page 249 of 472 rej09b0160-0200 mov.b #b'11101111, r0l only the bit to be cleared is 0 and the other bits are all set to 1. mov.b r0l,@tsr 10. note on writing to the toa0 to tod0 bits and the toa1 to tod1 bits in tocr: the toa0 to tod0 bits and the toa1 to tod1 bits in tocr decide the value of the ftio pin, which is output until the first compare match occurs. once a compare match occurs and this compare match changes the values of ftioa0 to ftiod0 and ftioa1 to ftiod1 output, the values of the ftioa0 to ftiod0 and ftioa1 to ftiod1 pin output and the values read from the toa0 to tod0 and toa1 to tod1 bits may differ. moreover, when the writing to tocr and the generation of the compare match a0 to d0 and a1 to d1 occur at the same timing, the writing to tocr has the priority. thus, output change due to the compare match is not reflected to the ftioa0 to ftio d0 and ftioa1 to ftiod1 pins. therefore, when bit manipulation instruction is used to write to tocr, the values of the ftioa0 to ftiod0 and ftioa1 to ftiod1 pin output may result in an unexpected result. when tocr is to be written to while compare match is oper ating, stop the counter once before accessing to tocr, read the port 6 state to reflect the va lues of ftioa0 to ftiod0 and ftioa1 to ftiod1 output, to toa0 to tod0 and toa1 to tod1, and then restart the counter. figure 13.59 shows an example when the compare match and the bit manipulation instruction to tocr occur at the same timing. section 13 timer z rev. 2.00 sep. 23, 2005 page 250 of 472 rej09b0160-0200 compare match signal b0 ftiob0 pin tocr write signal set value bit tocr 000 00110 765 43210 tod1 toc1 tob1 toa1 tod0 toc0 tob0 toa0 expected output remains high because the 1 writing to tob has priority tocr has been set to h'06. compare match b0 and compare match c0 are used. the ftiob0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match b0. when bclr#2, @tocr is executed to clear the toc0 bit (the ftioc0 signal is low) and compare match b0 occurs at the same timing as shown below, the h'02 writing to tocr has priority and compare match b0 does not drive the ftiob0 signal low; the ftiob0 signal remains high. bclr#2, @tocr (1) tocr read operation: read h'06 (2) modify operation: modify h'06 to h'02 (3) write operation to tocr: write h'02 figure 13.59 when compa re match and bit manipulation instruction to tocr occur at the same timing section 14 watchdog timer wdt0110a_000020020200 rev. 2.00 sep. 23, 2005 page 251 of 472 rej09b0160-0200 section 14 watchdog timer the watchdog timer is an 8-bit timer that can gene rate an internal reset signal for this lsi if a system crash prevents the cpu from writing to th e timer counter, thus allowing it to overflow. the block diagram of the watchdog timer is shown in figure 14.1. internal reset signal pss tcwd tmwd tcsrwd internal data bus [legend] tcsrwd: timer control/status register wd tcwd: timer counter wd pss: prescaler s tmwd: timer mode register wd internal oscillator clk figure 14.1 block diagram of watchdog timer 14.1 features ? selectable from nine counter input clocks. eight clock sources ( /64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the internal oscillator can be selected as the timer-c ounter clock. when the internal oscillator is selected, it can operate as the watc hdog timer in any operating mode. ? reset signal generated on counter overflow an overflow period of 1 to 256 times the selected clock can be set. section 14 watchdog timer rev. 2.00 sep. 23, 2005 page 252 of 472 rej09b0160-0200 14.2 register descriptions the watchdog timer has the following registers. ? timer control/status register wd (tcsrwd) ? timer counter wd (tcwd) ? timer mode register wd (tmwd) 14.2.1 timer control/stat us register wd (tcsrwd) tcsrwd performs the tcsrwd and tcwd writ e control. tcsrwd also controls the watchdog timer operation and indicates the operatin g state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1. section 14 watchdog timer rev. 2.00 sep. 23, 2005 page 253 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 wdon 0 r/w watchdog timer on tcwd starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when 1 is written to the wdon bit while writing 0 to the b2wi bit when the tcsrwe bit=1 [clearing condition] ? reset by res pin ? when 0 is written to the wdon bit while writing 0 to the b2wi when the tcsrwe bit=1 1 b0wi 1 r/w bit 0 write inhibit this bit can be written to the wrst bit only when the write value of the b0wi bit is 0. this bit is always read as 1. 0 wrst 0 r/w watchdog timer reset [setting condition] when tcwd overflows and an internal reset signal is generated [clearing condition] ? reset by res pin ? when 0 is written to the wrst bit while writing 0 to the b0wi bit when the tcsrwe bit=1 14.2.2 timer coun ter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd is set to 1. tcwd is initialized to h'00. section 14 watchdog timer rev. 2.00 sep. 23, 2005 page 254 of 472 rej09b0160-0200 14.2.3 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 1000: internal clock: counts on /64 1001: internal clock: counts on /128 1010: internal clock: counts on /256 1011: internal clock: counts on /512 1100: internal clock: counts on /1024 1101: internal clock: counts on /2048 1110: internal clock: counts on /4096 1111: internal clock: counts on 8192 0xxx: internal oscillator for the internal oscillator overflow periods, see section 20, electrical characteristics. [legend] x: don't care. section 14 watchdog timer rev. 2.00 sep. 23, 2005 page 255 of 472 rej09b0160-0200 14.3 operation the watchdog timer is provided with an 8-bit counter. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrwd is set to 1, tcwd begins counting up. (to operate the watchdog timer, two write accesses to tcsrwd are required.) when a clock pulse is input after the tcwd count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 256 osc clock cycles. tcwd is a writable counter, and when a value is set in tc wd, the count-up starts from that value. an overflow period in the range of 1 to 256 input cl ock cycles can therefore be set, according to the tcwd set value. figure 14.2 shows an example of watchdog timer operation. example: with 30ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 256 osc clock cycles therefore, 256 ? 15 = 241 (h'f1) is set in tcw. figure 14.2 watchdog timer operation example section 14 watchdog timer rev. 2.00 sep. 23, 2005 page 256 of 472 rej09b0160-0200 section 15 14-bit pwm pwm1400a_000120030300 rev. 2.00 sep. 23, 2005 page 257 of 472 rej09b0160-0200 section 15 14-bit pwm the 14-bit pwm is a pulse division type pwm that can be used for electronic tuner control, etc. figure 15.1 shows a block diagram of the 14-bit pwm. 15.1 features ? choice of two conversion periods a conversion period of 32768/ with a minimum modulation width of 2/ , or a conversion period of 16384/ with a minimum modulation width of 1/ , can be selected. ? pulse division method for less ripple pwcr: pwm control register [legend] internal data bus pwdrl: pwm data register l pwdru: pwm data register u pwm: pwm output pin pwcr pwdrl pwdru pwm pwm waveform generator /4 /2 figure 15.1 block diagram of 14-bit pwm section 15 14-bit pwm rev. 2.00 sep. 23, 2005 page 258 of 472 rej09b0160-0200 15.2 input/output pin table 15.1 shows the 14-bit pwm pin configuration. table 15.1 pin configuration name abbreviation i/o function 14-bit pwm square-wave output pwm out put 14-bit pwm square-wave output pin 15.3 register descriptions the 14-bit pwm has the following registers. ? pwm control register (pwcr) ? pwm data register u (pwdru) ? pwm data register l (pwdrl) 15.3.1 pwm control register (pwcr) pwcr selects the conversion period. bit bit name initial value r/w description 7 to 1 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 0 pwcr0 0 r/w clock select 0: the input clock is /2 (t = 2/ ) ? the conversion period is 16384/ , with a minimum modulation width of 1/ 1: the input clock is /4 (t = 4/ ) ? the conversion period is 32768/ , with a minimum modulation width of 2/ [legend] t : period of pwm clock input section 15 14-bit pwm rev. 2.00 sep. 23, 2005 page 259 of 472 rej09b0160-0200 15.3.2 pwm data registers u and l (pwdru, pwdrl) pwdru and pwdrl indicate high level width in one pwm waveform cycle. pwdru and pwdrl are 14-bit write-only registers, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. when read, all b its are always read as 1. both pwdru and pwdrl are accessible only in bytes. note that th e operation is not guaranteed if word access is performed. wh en 14-bit data is written in pwdru and pwdrl, the contents are latched in the pwm waveform generator and the pwm waveform generation data is updated. when writing the 14-bit data, the order is as follows: pwdrl to pwdru. pwdru and pwdrl are initialized to h'c000. 15.4 operation when using the 14-bit pwm, set the registers in this sequence: 1. set the pwm bit in the port mode register 1 (pmr1) to set the p11/pwm pin to function as a pwm output pin. 2. set the pwcr0 bit in pwcr to select a conversion period of either. 3. set the output waveform data in pwdru and pwdrl. be sure to write byte data first to pwdrl and then to pwdru. when the data is written in pwdru, the contents of these registers are latched in the pwm waveform generator, and the pwm waveform generation data is updated in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 15.2. the total high-level width during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be expressed as follows: t h = (data value in pwdru and pwdrl + 64) t /2 where t is the period of pwm clock input: 2/ (bit pwcr0 = 0) or 4/ (bit pwcr0 = 1). if the data value in pwdru and pwdrl is from h'ffc0 to h'ffff, the pwm output stays high. when the data value is h'c000, t h is calculated as follows: t h = 64 t /2 = 32 t section 15 14-bit pwm rev. 2.00 sep. 23, 2005 page 260 of 472 rej09b0160-0200 t h64 t h63 t h3 t h2 t h1 t h = t h1 + t h2 + t h3 + ... + t h64 t f1 = t f2 = t f3 = ... = t f64 t f1 t f2 t f63 t f64 conversion period figure 15.2 waveform output by 14-bit pwm section 16 serial communication interface 3 (sci3) sci0011a_000020020200 rev. 2.00 sep. 23, 2005 page 261 of 472 rej09b0160-0200 section 16 serial communi cation interface 3 (sci3) this lsi includes a serial communication interface 3 (sci3), which has independent two channels. the sci3 can handle both asynchronous and clocked synchronous serial communication. in asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receive r/transmitter (uart) or an asynchronous communication interf ace adapter (acia). a function is also provided for serial communication between processors (mu ltiprocessor communication function). table 16.1 shows the sci3 channel configuration and figure 16.1 shows a block diagram of the sci3. since pin functions are identical for each of the two channels (sci3 and sci3_2), separate explanations are not given in this section. 16.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? external clock or on-chip baud rate generator can be selected as a transfer clock source. ? six interrupt sources transmit-end, transmit-data-empty , receive-data-full, ove rrun error, framing error, and parity error. asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by read ing the rxd pin level directly in the case of a framing error section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 262 of 472 rej09b0160-0200 clocked synchronous mode ? data length: 8 bits ? receive error detecti on: overrun errors table 16.1 channel configuration channel abbreviation pin re gister register address smr h'ffa8 brr h'ffa9 scr3 h'ffaa tdr h'ffab ssr h'ffac rdr h'ffad rsr ? channel 1 sci3 * sck3 rxd txd tsr ? smr_2 h'f740 brr_2 h'f741 scr3_2 h'f742 tdr_2 h'f743 ssr_2 h'f744 rdr_2 h'f745 rsr_2 ? channel 2 sci3_2 sck3_2 rxd_2 txd_2 tsr_2 ? note: * the channel 1 of the sci3 is used in on-board programming mode by boot mode. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 263 of 472 rej09b0160-0200 clock txd rxd sck 3 brr smr scr3 ssr tdr rdr tsr rsr transmit/receive control circuit internal data bus [legend] rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter interrupt request (tei, txi, rxi, eri) internal clock (?/64, ?/16, ?/4, ?) external clock brc baud rate generator figure 16.1 block diagram of sci3 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 264 of 472 rej09b0160-0200 16.2 input/output pins table 16.2 shows the sci3 pin configuration. table 16.2 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sc i3 clock input/output sci3 receive data input rxd i nput sci3 receive data input sci3 transmit data output txd output sci3 transmit data output 16.3 register descriptions the sci3 has the following registers for each channel. ? receive shift register (rsr) ? receive data register (rdr) ? transmit shift register (tsr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register 3 (scr3) ? serial status register (ssr) ? bit rate register (brr) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 265 of 472 rej09b0160-0200 16.3.1 receive shi ft register (rsr) rsr is a shift register that is us ed to receive serial data input fr om the rxd pin and convert it into parallel data. when one frame of data has been r eceived, it is transferre d to rdr automatically. rsr cannot be directly accessed by the cpu. 16.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data. when the sci3 has receiv ed one frame of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a d ouble buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. 16.3.3 transmit shift register tsr (sci3) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data fr om tdr to tsr automatically, then sends the data that starts from the lsb to the txd pin . tsr cannot be directly accessed by the cpu. 16.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sc i3 detects that tsr is empty, it transfers the tr ansmit data written in tdr to tsr an d starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transm ission of one-frame data, the sci3 transfers the written data to tsr to continue transmission . to achieve reliable serial transmission, write transmit data to tdr only once after confirming th at the tdre bit in ssr is set to 1. tdr is initialized to h'ff. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 266 of 472 rej09b0160-0200 16.3.5 serial mode register (smr) smr is used to set the sci3?s serial transfer format and select the baud rate generator clock source. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid in mult iprocessor mode. in clocked synchronous mode, clear this bit to 0. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 267 of 472 rej09b0160-0200 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 16.3.8, bit rate register (brr). n is the decimal represent ation of the value of n in brr (see section 16.3.8, bit rate register (brr)). 16.3.6 serial control register 3 (scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. for details on interrupt requests, refer to section 16.7, interrupts. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 268 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is disabled. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 16.6, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, tei interrupt request is enabled. 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. ? asynchronous mode 00: on-chip baud rate generator 01: on-chip baud rate generator outputs a clock of the same frequency as the bit rate from the sck3 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck3 pin. 11:reserved ? clocked synchronous mode 00: on-chip clock (sck3 pin functions as clock output) 01: reserved 10: external clock (sck3 pin functions as clock input) 11: reserved section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 269 of 472 rej09b0160-0200 16.3.7 serial status register (ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr3 is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when data is read from rdr 5 oer 0 r/w overrun error [setting condition] ? when an overrun error occurs in reception [clearing condition] ? when 0 is written to oer after reading oer = 1 4 fer 0 r/w framing error [setting condition] ? when a framing error occurs in reception [clearing condition] ? when 0 is written to fer after reading fer = 1 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 270 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr3 is 0 ? when tdre = 1 at transmission of the last bit of a 1- frame serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 271 of 472 rej09b0160-0200 16.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. the initial value of brr is h'ff. table 16.3 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 16.4 show s the maximum bit rate for each frequency in asynchronous mode. the values shown in both ta bles 16.3 and 16.4 are values in active (high- speed) mode. table 16.5 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in clocked synchronous mode. the values shown in table 16.5 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = 64 2 2n?1 b 10 6 ? 1 error (%) = ? 1 100 ? ? ? ? ? ? 10 6 (n + 1) b 64 2 2n?1 [clocked synchronous mode] n = 8 2 2n?1 b 10 6 ? 1 [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: csk1 and csk0 settings in smr (0 n 3) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 272 of 472 rej09b0160-0200 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) 110 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 8.51 0 3 0.00 0 3 1.73 [legend] ? : a setting is available but error occurs section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 273 of 472 rej09b0160-0200 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 6 6.144 7.3728 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.00 0 95 0.00 4800 0 38 0.16 0 39 0.00 0 47 0.00 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 31250 0 5 0.00 0 5 2.40 0 6 5.33 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 274 of 472 rej09b0160-0200 operating frequency (mhz) 8 9.8304 10 12 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 141 0.03 2 174 ?0.26 2 177 ?0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 ?1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 ?2.34 31250 0 7 0.00 0 9 ?1.70 0 9 0.00 0 11 0.00 38400 0 6 -6.99 0 7 0.00 0 7 1.73 0 9 ?2.34 [legend] ? : a setting is availabl e but error occurs. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 275 of 472 rej09b0160-0200 table 16.3 examples of brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 12.888 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 0 9 0.00 ? ? ? 0 11 0.00 0 12 0.16 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 276 of 472 rej09b0160-0200 operating frequency (mhz) 18 bit rate (bit/s) n n error (%) 110 3 79 ?0.12 150 2 233 0.16 300 2 116 0.16 600 1 233 0.16 1200 1 116 0.16 2400 0 233 0.16 4800 0 116 0.16 9600 0 58 ?0.96 19200 0 28 1.02 31250 0 17 0.00 38400 0 14 ?2.34 [legend] ?: a setting is available but error occurs. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 277 of 472 rej09b0160-0200 table 16.4 maximum bit rate for ea ch frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 278 of 472 rej09b0160-0200 table 16.5 examples of brr settings for va rious bit rates (clocked synchronous mode) (1) operating frequency (mhz) 4 8 10 16 bit rate (bit/s) n n n n n n n n 110 ? ? ? ? ? ? 250 2 249 3 124 ? ? 3 249 500 2 124 2 249 ? ? 3 124 1k 1 249 2 124 ? ? 2 249 2.5k 1 99 1 199 1 249 2 99 5k 0 199 1 99 1 124 1 199 10k 0 99 0 199 0 249 1 99 25k 0 39 0 79 0 99 0 159 50k 0 19 0 39 0 49 0 79 100k 0 9 0 19 0 24 0 39 250k 0 3 0 7 0 9 0 15 500k 0 1 0 3 0 4 0 7 1m 0 0 * 0 1 ? ? 0 3 2m 0 0 * ? ? 0 1 2.5m 0 0 * ? ? 4m 0 0 * [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 279 of 472 rej09b0160-0200 table 16.5 examples of brr settings for va rious bit rates (clocked synchronous mode) (2) operating frequency (mhz) 18 bit rate (bit/s) n n 110 ? ? 250 ? ? 500 3 140 1k 3 69 2.5k 2 112 5k 1 224 10k 1 112 25k 0 179 50k 0 89 100k 0 44 250k 0 17 500k 0 8 1m 0 4 2m ? ? 2.5m ? ? 4m ? ? [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 280 of 472 rej09b0160-0200 16.4 operation in asynchronous mode figure 16.2 shows the general format for asynchronous serial communication. one character (or frame) consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). inside the sci3, the tran smitter and receiver are independent units, enabling full-dupl ex. both the transmitter and th e receiver also have a double- buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 16.2 data format in asynchronous communication 16.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as th e sci3?s serial clock, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 16.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 16.3 relationship between output clock and transfer data phase (asynchronous mode)(example with 8-bit data, parity, two stop bits) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 281 of 472 rej09b0160-0200 16.4.2 sci3 initialization before transmitting and receiving data, you should first clear the te and re bits in scr3 to 0, then initialize the sci3 as described below. wh en the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 282 of 472 rej09b0160-0200 16.4.3 data transmission figure 16.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, th e sci3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at th is time, a txi interrupt request is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the tei e bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 16.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1d0d1d70/11 11 0d0d1 d70/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 16.5 example of sci3 transmission in asynchronous mode (8-bit data, parity, one stop bit) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 283 of 472 rej09b0160-0200 no section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 284 of 472 rej09b0160-0200 16.4.4 serial data reception figure 16.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci3 operat es as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi inte rrupt routine r eads the receive data transferred to rdr before reception of the next receive data has been completed. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1d0d1d70/11 01 0d0d1 d70/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 16.7 example of sci3 reception in asynchronous mode (8-bit data, parity, one stop bit) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 285 of 472 rej09b0160-0200 table 16.6 shows the states of th e ssr status flags and receive da ta handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 16.8 shows a sample flow chart for serial data reception. table 16.6 ssr status flag s and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the stat e it had before data reception. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 286 of 472 rej09b0160-0200 yes section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 287 of 472 rej09b0160-0200 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 288 of 472 rej09b0160-0200 16.5 operation in clocked synchronous mode figure 16.9 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data co nsists of the 8-bit data starti ng from the lsb. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next. in clocked synchronous mo de, the sci3 receives data in synchronous with the rising edge of the synchronization clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and receiver are independent units, enabling full- duplex communication thro ugh the use of a common clock. bo th the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling conti nuous data transfer. don?t care don?t care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 16.9 data format in clocked synchronous communication 16.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the synchronization clock is output from the sck3 pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 16.5.2 sci3 initialization before transmitting and receiving data, the sci3 sh ould be initialized as described in a sample flowchart in figure 16.4. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 289 of 472 rej09b0160-0200 16.5.3 serial data transmission figure 16.10 shows an example of sci3 operation for transmission in clocked synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci3 recognizes that data has been written to tdr, and transf ers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts tr ansmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd pin. 4. the sci3 checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck3 pin is fixed high at the end of transmission. figure 16.11 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a r eceive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 290 of 472 rej09b0160-0200 serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 16.10 example of sci3 transmission in clocked synchronous mode section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 291 of 472 rej09b0160-0200 no section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 292 of 472 rej09b0160-0200 16.5.4 serial data reception (clocked synchronous mode) figure 16.12 shows an example of sci3 operation for reception in clocked synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. the sci3 stores the receive data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, re ceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 16.12 example of sci3 reception in clocked synchronous mode reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 16.13 shows a sample flow chart for serial data reception. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 293 of 472 rej09b0160-0200 yes section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 294 of 472 rej09b0160-0200 16.5.5 simultaneous serial data transmission and reception figure 16.14 shows a samp le flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous seri al data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode , after checking that the sci3 has finished reception, clear re to 0. then after checking th at the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 295 of 472 rej09b0160-0200 yes section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 296 of 472 rej09b0160-0200 16.6 multiprocessor communication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by as ynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor commun ication is performed, each receiving st ation is addressed by a unique id code. the serial communication cy cle consists of two component cy cles; an id transmission cycle that specifies the receiving station, and a data transmission cycl e. the multiprocessor bit is used to differentiate between the id tr ansmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transm ission cycle; if the mul tiprocessor bit is 0, the cycle is a data transmission cycle. figure 16.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with wh ich it wants to perform serial co mmunication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor b it is received, the receiving statio n compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data w ith a 1 multiprocessor bi t is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer, to 1, are inhibited until data with a 1 mu ltiprocessor bit is received. on reception of a receive character w ith a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 297 of 472 rej09b0160-0200 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend mpb: multiprocessor bit figure 16.15 example of in ter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 298 of 472 rej09b0160-0200 16.6.1 multiprocessor seri al data transmission figure 16.16 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 299 of 472 rej09b0160-0200 no section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 300 of 472 rej09b0160-0200 16.6.2 multiprocessor s erial data reception figure 16.17 shows a sample flowchart for multiproces sor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci3 operations are the same as those in asynchronous mode. figure 16.18 shows an example of sci3 oper ation for multiprocesso r format reception. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 301 of 472 rej09b0160-0200 yes section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 302 of 472 rej09b0160-0200 section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 303 of 472 rej09b0160-0200 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 16.18 example of sci3 r eception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit) section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 304 of 472 rej09b0160-0200 16.7 interrupts sci3 creates the following six interrupt requests: transmission end, transm it data empty, receive data full, and receive errors (ove rrun error, framing error, and pa rity error). tabl e 16.7 shows the interrupt sources. table 16.7 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to tdr, a txi interr upt request is generated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possib le to make use of the most of these interrupt requests efficiently by transferring the transmit da ta to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi an d tei), set the enable bits (tie and teie) that correspond to these in terrupt requests to 1, after transf erring the transmit data to tdr. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 305 of 472 rej09b0160-0200 16.8 usage notes 16.8.1 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 16.8.2 mark state and break sending when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and clear pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 16.8.3 receive error flags and transmit op erations (clocked synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. section 16 serial communication interface 3 (sci3) rev. 2.00 sep. 23, 2005 page 306 of 472 rej09b0160-0200 16.8.4 receive data sampling timing and recept ion margin in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 16 .19. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) [legend] n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute va lue of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 16.19 receive data sampling timing in asynchronous mode section 17 i 2 c bus interface 2 (iic2) ifiic10a_000020020200 rev. 2.00 sep. 23, 2005 page 307 of 472 rej09b0160-0200 section 17 i 2 c bus interface 2 (iic2) the i 2 c bus interface 2 conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register co nfiguration that controls the i 2 c bus differs partly from the philips configuration, however. figure 17.1 shows a block diagram of the i 2 c bus interface 2. figure 17.2 shows an example of i/o pin connections to external circuits. 17.1 features ? selection of i 2 c format or clocked synchronous serial format ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmi ssion/reception can be performed. i 2 c bus format ? start and stop conditions generated automatically in master mode ? selection of acknowledge output levels when receiving ? automatic loading of acknowledge bit when transmitting ? bit synchronization/wait function in master mode, the state of scl is monitored per bit, and the timing is synchronized automatically. if transmission/reception is not yet possible, set the scl to low un til preparations are completed. ? six interrupt sources transmit data empty (including slave-address matc h), transmit end, receive data full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, scl and sda pins, function as nmos open-drain outputs when the bus drive function is selected. clocked synchronous format ? four interrupt sources transmit-data-empty, transmit-end, receive-data-full, and overrun error section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 308 of 472 rej09b0160-0200 scl iccr1 transfer clock generation circuit address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccr2 icmr icsr icier icdrr icdrs icdrt i 2 c bus control register 1 i 2 c bus control register 2 i 2 c bus mode register i 2 c bus status register i 2 c bus interrupt enable register i 2 c bus transmit data register i 2 c bus receive data register i 2 c bus shift register slave address register [legend] iccr1: iccr2: icmr: icsr: icier: icdrt: icdrr: icdrs: sar: sar sda internal data bus figure 17.1 block diagram of i 2 c bus interface 2 section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 309 of 472 rej09b0160-0200 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 17.2 external circu it connections of i/o pins section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 310 of 472 rej09b0160-0200 17.2 input/output pins table 17.1 summarizes the input/output pins used by the i 2 c bus interface 2. table 17.1 i 2 c bus interface pins name abbreviation i/o function serial clock scl i/o iic se rial clock input/output serial data sda i/o iic serial data input/output note: scl and sda pins are nmos open drains, when the bus drive function is selected. however the voltage which can be applied to these pins depends on the voltage of the power supply (v cc ) of this lsi. 17.3 register descriptions the i 2 c bus interface 2 has the following registers: ? i 2 c bus control register 1 (iccr1) ? i 2 c bus control register 2 (iccr2) ? i 2 c bus mode register (icmr) ? i 2 c bus interrupt enable register (icier) ? i 2 c bus status register (icsr) ? i 2 c bus slave address register (sar) ? i 2 c bus transmit data register (icdrt) ? i 2 c bus receive data register (icdrr) ? i 2 c bus shift register (icdrs) section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 311 of 472 rej09b0160-0200 17.3.1 i 2 c bus control register 1 (iccr1) iccr1 enables or disables the i 2 c bus interface 2, controls transm ission or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted. (scl and sda pins are set to port function.) 1: this bit is enabled for transfer operations. (scl and sda pins are bus drive state.) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. after data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to sar and the eighth bit is 1, trs is automatically set to 1. if an overrun error occurs in master mode with the clock synchronous serial format, mst is cleared to 0 and slave receive mode is entered. operating modes are described below according to mst and trs combination. when clocked synchronous serial format is selected and mst is 1, clock is output. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 312 of 472 rej09b0160-0200 bit bit name initial value r/w description 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits should be set according to the necessary transfer rate (see table 17.2) in master mode. in slave mode, these bits are used fo r reservation of the setup time in transmit mode. the time is 10 t cyc when cks3 = 0 and 20 t cyc when cks3 = 1. table 17.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 18 mhz 0 /28 179 khz 286 khz 357 khz 571 khz 642 khz 0 1 /40 125 khz 200 khz 250 khz 400 khz 450 khz 0 /48 104 khz 167 khz 208 khz 333 khz 375 khz 0 1 1 /64 78.1 khz 125 khz 156 khz 250 khz 281 khz 0 /80 62.5 khz 100 khz 125 khz 200 khz 225 khz 0 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 180 khz 0 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 160 khz 0 1 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 140 khz 0 /56 89.3 khz 143 khz 179 khz 286 khz 321 khz 0 1 /80 62.5 khz 100 khz 125 khz 200 khz 225 khz 0 /96 52.1 khz 83.3 khz 104 khz 167 khz 187 khz 0 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 140 khz 0 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 112 khz 0 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 90 khz 0 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 80.3 khz 1 1 1 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 70.3 khz section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 313 of 472 rej09b0160-0200 17.3.2 i 2 c bus control register 2 (iccr2) iccr1 issues start/stop conditions, manipulates the sda pin, monitors the scl pin, and controls reset in the control part of the i 2 c bus interface 2. bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit enables to confirm whether the i 2 c bus is occupied or released and to issue start/stop conditions in master mode. with the clocked synchronous serial format, this bit has no meaning. with the i 2 c bus format, this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assu ming that the stop condition has been issued. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re- transmitting a start condition. write 0 in bbsy and 0 in scp to issue a stop condition. to issue start/stop conditions, use the mov instruction. 6 scp 1 w start/stop issue condition disable the scp bit controls the iss ue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r/w sda output value control this bit is used with sdaop when modifying output level of sda. this bit should not be manipulated during transfer. 0: when reading, sda pin outputs low. when writing, sda pin is changed to output low. 1: when reading, sda pin outputs high. when writing, sda pin is changed to output hi-z (outputs high by external pull-up resistance). section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 314 of 472 rej09b0160-0200 bit bit name initial value r/w description 4 sdaop 1 r/w sdao write protect this bit controls change of output level of the sda pin by modifying the sdao bit. to change the output level, clear sdao and sdaop to 0 or set sdao to 1 and clear sdaop to 0 by the mov instruction. this bit is always read as 1. 3 sclo 1 r this bit monitors scl output level. when sclo is 1, scl pin outputs high. when sclo is 0, scl pin outputs low. 2 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 1 iicrst 0 r/w iic control part reset this bit resets the control part except for i 2 c registers. if this bit is set to 1 when hang-up occurs because of communication failure during i 2 c operation, i 2 c control part can be reset without setting ports and initializing registers. 0 ? 1 ? reserved this bit is always read as 1, and cannot be modified. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 315 of 472 rej09b0160-0200 17.3.3 i 2 c bus mode register (icmr) icmr selects whether the msb or lsb is transfer red first, performs master mode wait control, and selects the tran sfer bit count. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 wait 0 r/w wait insertion bit in master mode with the i 2 c bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. when wait is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the setting of this bit is invalid in slave mode with the i 2 c bus format or with the clocked synchronous serial format. 5, 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 bcwp 1 r/w bc write protect this bit controls the bc2 to bc0 modifications. when modifying bc2 to bc0, this bit should be cleared to 0 and use the mov instruction. in clock synchronous serial mode, bc should not be modified. 0: when writing, values of bc2 to bc0 are set. 1: when reading, 1 is always read. when writing, settings of bc2 to bc0 are invalid. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 316 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. when read, the remaining number of transfer bits is indicated. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl pin is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. with the clock synchronous serial format, these bits should not be modified. i 2 c bus format clock synchronous serial format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 317 of 472 rej09b0160-0200 17.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and conf irms acknowledge bits to be received. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit dat a empty interrupt (txi). 0: transmit data empty interru pt request (txi) is disabled. 1: transmit data empty interru pt request (txi) is enabled. 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) at the rising of the nint h clock while the tdre bit in icsr is 1. tei can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt request (tei) is disabled. 1: transmit end interrupt request (tei) is enabled. 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive data full interrupt request (rxi) and the overrun error interrupt request (eri) with the clocked synchronous format, when a receive data is transferred fr om icdrs to icdrr and the rdrf bit in icsr is set to 1. rxi can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clocked synchronous format are disabled. 1: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clocked synchronous format are enabled. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 318 of 472 rej09b0160-0200 bit bit name initial value r/w description 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt request (naki) and the overrun error (setting of the ove bit in icsr) interrupt request (eri) with the clocked synchronous format, when the nackf and al bits in icsr are set to 1. naki can be canceled by clearing the nackf, ove, or nakie bit to 0. 0: nack receive interrupt request (naki) is disabled. 1: nack receive interrupt request (naki) is enabled. 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt request (stpi) is disabled. 1: stop condition detection interrupt request (stpi) is enabled. 2 acke 0 r/w acknowledge bit judgement select 0: the value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: if the receive acknowledge bit is 1, continuous transfer is halted. 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit specif ies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 319 of 472 rej09b0160-0200 17.3.5 i 2 c bus status register (icsr) icsr performs confirmation of interrupt request flags and status. bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting condition] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when trs is set ? when a start condition (including re-transfer) has been issued ? when transmit mode is entered from receive mode in slave mode [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when data is written to icdrt with an instruction 6 tend 0 r/w transmit end [setting conditions] ? when the ninth clock of scl rises with the i 2 c bus format while the tdre flag is 1 ? when the final bit of transmit frame is sent with the clock synchronous serial format [clearing conditions] ? when 0 is written in tend after reading tend = 1 ? when data is written to icdrt with an instruction 5 rdrf 0 r/w receive data register full [setting condition] ? when a receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when icdrr is read with an instruction section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 320 of 472 rej09b0160-0200 bit bit name initial value r/w description 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is 1 [clearing condition] ? when 0 is written in nackf after reading nackf = 1 3 stop 0 r/w stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in sar [clearing condition] ? when 0 is written in stop after reading stop = 1 section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 321 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 al/ove 0 r/w arbitration lost flag/overrun error flag this flag indicates that arbitration was lost in master mode with the i 2 c bus format and that the final bit has been received while rdrf = 1 with the clocked synchronous format. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? when the sda pin outputs high in master mode while a start condition is detected ? when the final bit is received with the clocked synchronous format while rdrf = 1 [clearing condition] ? when 0 is written in al/ove after reading al/ove=1 1 aas 0 r/w slave addr ess recognition flag in slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode. [clearing condition] ? when 0 is written in aas after reading aas=1 section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 322 of 472 rej09b0160-0200 bit bit name initial value r/w description 0 adz 0 r/w general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing conditions] ? when 0 is written in adz after reading adz=1 17.3.6 slave address register (sar) sar selects the communica tion format and sets the slave address. when the chip is in slave mode with the i 2 c bus format, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the ch ip operates as the slave device. bit bit name initial value r/w description 7 to 1 sva6 to sva0 all 0 r/w slave address 6 to 0 these bits set a unique address in bits sva6 to sva0, differing form the addresses of other slave devices connected to the i 2 c bus. 0 fs 0 r/w format select 0: i 2 c bus format is selected. 1: clocked synchronous seri al format is selected. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 323 of 472 rej09b0160-0200 17.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects the space in the shift register (icdrs), it transfers th e transmit data which is written in icdrt to icdrs and starts transferring data. if the next transfer data is written to icdrt during transferring data of icdrs, conti nuous transfer is possible. if the mls bit of icmr is set to 1 and when the data is written to icdrt, the msb/lsb inverted data is read. the initial value of icdrt is h'ff. 17.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit register that stores the receiv e data. when data of one byte is received, icdrr transfers the receive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only register, therefore the cpu cannot write to this regist er. the initial value of icdrr is h'ff. 17.3.9 i 2 c bus shift register (icdrs) icdrs is a register that is used to transfer/receive data. in transm ission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr after data of one byte is received. this register cannot be read directly from the cpu. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 324 of 472 rej09b0160-0200 17.4 operation the i 2 c bus interface can communicate either in i 2 c bus mode or clocked synchronous serial mode by setting fs in sar. 17.4.1 i 2 c bus format figure 17.3 shows the i 2 c bus formats. figure 17.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (fs = 0) (b) i 2 c bus format (start condition retransmission, fs = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 17.3 i 2 c bus formats sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a figure 17.4 i 2 c bus timing section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 325 of 472 rej09b0160-0200 [legend] s: start condition. the master device drives sda from high to low while scl is high. sla: slave address r/ w : indicates the direction of data transfer: fr om the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda to low. data: transfer data p: stop condition. the master device drives sda from low to high while scl is high. 17.4.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for ma ster transmit mode operation timing, refer to figures 17.5 and 17.6. the transmission procedure and operations in master transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. read the bbsy flag in iccr2 to confirm that the bus is free. set the mst and trs bits in iccr1 to select master transmit mode. then , write 1 to bbsy and 0 to scp using mov instruction. (start condition issued) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte data show the slave address and r/ w ) to icdrt. at this time, tdre is automatically cleared to 0, and data is transferred from icdrt to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in icier, and confirm that the slave device has been selected. then, write second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue the stop condition. to issue the stop condition, write 0 to bbsy and scp using mov instruction. scl is fixed low until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wait for nack (nackf in icsr = 1) from the receive device while acke in icier is 1. then , issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, the operation returns to the slave receive mode. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 326 of 472 rej09b0160-0200 tdre scl (master output) sda (master output) sda (slave output) tend [5] write data to icdrt (third byte) icdrt icdrs [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) user processing 1 bit 7 slave address address + r/ w data 1 data 1 data 2 address + r/ w bit 6 bit 7 bit 6 bit 5bit 4bit 3bit 2bit 1bit 0 212 3456789 a r/ w figure 17.5 master transmit mode operation timing (1) tdre [6] issue stop condition. clear tend. [7] set slave receive mode tend icdrt icdrs 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 data n data n bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [5] write data to icdrt user processing figure 17.6 master transmit mode operation timing (2) section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 327 of 472 rej09b0160-0200 17.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. for master receive mode operation timing, refer to figures 17.7 and 17.8. the reception procedure and operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccr1 to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icdrr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. the master device outputs the level specified by ackbt in icier to sda, at the 9th receive clock pulse. 3. after the reception of first frame data is complete d, the rdrf bit in icst is set to 1 at the rise of 9th receive clock pulse. at this time, the r eceive data is read by reading icdrr, and rdrf is cleared to 0. 4. the continuous reception is performed by reading icdrr every time rdrf is set. if 8th receive clock pulse falls after reading icdrr by the other processing while rdrf is 1, scl is fixed low until icdrr is read. 5. if next frame is the last receive data, set th e rcvd bit in iccr1 to 1 before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at rise of th e 9th receive clock pulse, issue the stage condition. 7. when the stop bit in icsr is set to 1, read icdrr. then clear the rcvd bit to 0. 8. the operation returns to the slave receive mode. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 328 of 472 rej09b0160-0200 tdre tend icdrs icdrr [1] clear tdre after clearing tend and trs [2] read icdrr (dummy read) [3] read icdrr 1 a 21 3456789 9 a trs rdrf scl (master output) sda (master output) sda (slave output) bit 7 master transmit mode master receive mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing data 1 data 1 figure 17.7 master receive mode operation timing (1) section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 329 of 472 rej09b0160-0200 rdrf rcvd icdrs icdrr data n-1 data n data n data n-1 [5] read icdrr after setting rcvd [6] issue stop condition [7] read icdrr, and clear rcvd [8] set slave receive mode 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing figure 17.8 master receive mode operation timing (2) 17.4.4 slave transmit operation in slave transmit mode, the slave device outputs th e transmit data, while the master device outputs the receive clock and returns an acknowledge sign al. for slave transmit mode operation timing, refer to figures 17.9 and 17.10. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the leve l specified by ackbt in icier to sda, at the rise of the 9th clock pulse. at this time, if the 8th bit data (r/ w ) is 1, the trs and icsr bits in iccr1 are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing transmit data to icdrt every time tdre is set. 3. if tdre is set after writing la st transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when te nd is set, clear tend. 4. clear trs for the end processing, and read icdrr (dummy read). scl is free. 5. clear tdre. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 330 of 472 rej09b0160-0200 tdre tend icdrs icdrr 1 a 21 3456789 9 a trs icdrt scl (master output) slave receive mode slave transmit mode sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 data 1 data 1 data 2 data 3 data 2 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] write data to icdrt (data 1) [2] write data to icdrt (data 2) [2] write data to icdrt (data 3) user processing figure 17.9 slave transmit mode operation timing (1) section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 331 of 472 rej09b0160-0200 tdre data n tend icdrs icdrr 1 9 2345678 9 trs icdrt a scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 slave transmit mode slave receive mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a [3] clear tend [5] clear tdre [4] read icdrr (dummy read) after clearing trs user processing figure 17.10 slave transmit mode operation timing (2) section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 332 of 472 rej09b0160-0200 17.4.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. fo r slave receive mode ope ration timing, refer to figures 17.11 and 17.12. the reception procedure and operations in slave receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ac kbt in icier to sda, at the rise of the 9th clock pulse. at the same time, rdrf in icsr is set to read icdrr (d ummy read). (since the read data show the slave address and r/ w , it is not used.) 3. read icdrr every time rdrf is set. if 8th r eceive clock pulse falls while rdrf is 1, scl is fixed low until icdrr is read. the change of the acknowledge before reading icdrr, to be returned to the master device, is reflected to the next transmit frame. 4. the last byte data is read by reading icdrr. icdrs icdrr 12 1 345678 9 9 a a rdrf data 1 data 2 data 1 scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] read icdrr (dummy read) [2] read icdrr user processing figure 17.11 slave receive mode operation timing (1) section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 333 of 472 rej09b0160-0200 icdrs icdrr 12345678 9 9 a a rdrf scl (master output) sda (master output) sda (slave output) scl (slave output) user processing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 1 [3] set ackbt [3] read icdrr [4] read icdrr data 2 data 1 figure 17.12 slave receive mode operation timing (2) 17.4.6 clocked synchronous serial format this module can be operated with the clocked synchronous serial format, by setting the fs bit in sar to 1. when the mst bit in iccr1 is 1, the transfer clock output from scl is selected. when mst is 0, the external clock input is selected. (1) data transfer format figure 17.13 shows the clocked synchronous serial transfer format. the transfer data is output from the rise to the fa ll of the scl clock, and the data at the rising edge of the scl clock is guaranteed. the mls bit in icmr sets the order of data transfer, in either the msb first or lsb first. the output level of sda can be changed during the transfer wait, by the sdao bit in iccr2. sda bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 scl figure 17.13 clocked synchronous serial transfer format section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 334 of 472 rej09b0160-0200 (2) transmit operation in transmit mode, transmit data is output from sda, in synchronization with the fall of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for transmit mode operation timing, refer to figure 17.14. the transmission procedure and operations in transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. set the trs bit in iccr1 to select the transmit mode. then, tdre in icsr is set. 3. confirm that tdre has been set. then, write the transmit data to icdrt. the data is transferred from icdrt to icdrs, and td re is set automatically. the continuous transmission is performed by writing data to icdrt every time tdre is set. when changing from transmit mode to receive mode, clear trs while tdre is 1. 12 781 78 1 scl trs bit 0 data 1 data 1 data 2 data 3 data 2 data 3 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 sda (output) tdre icdrt icdrs user processing [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [2] set trs figure 17.14 transmit mode operation timing section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 335 of 472 rej09b0160-0200 (3) 6receive operation in receive mode, data is latched at the rise of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for receive mode operation timing, refer to figure 17.15. the reception pro cedure and operations in receiv e mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. when the transfer clock is output, set mst to 1 to start outputting the receive clock. 3. when the receive operation is completed, da ta is transferred from icdrs to icdrr and rdrf in icsr is set. when mst = 1, the ne xt byte can be received, so the clock is continually output. the continuous reception is performed by reading icdrr every time rdrf is set. when the 8th clock is risen wh ile rdrf is 1, the overrun is detected and al/ove in icsr is set. at this time, the pr evious reception data is retained in icdrr. 4. to stop receiving when mst = 1, set rcvd in iccr1 to 1, then read icdrr. then, scl is fixed high after receiving the next byte data. 12 781 7812 scl mst trs rdrf icdrs icdrr sda (input) bit 0 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 user processing data 1 data 1 data 2 data 2 data 3 [2] set mst (when outputting the clock) [3] read icdrr [3] read icdrr figure 17.15 receive mode operation timing section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 336 of 472 rej09b0160-0200 17.4.7 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 17.16 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d march detector internal scl or sda signal scl or sda input signal sampling clock sampling clock system clock period latch latch c q d figure 17.16 block di agram of noise conceler 17.4.8 example of use flowcharts in respective modes that use the i 2 c bus interface are shown in figures 17.17 to 17.20. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 337 of 472 rej09b0160-0200 bbsy=0 ? no tend=1 ? no yes start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] initialize set mst and trs in iccr1 to 1. write 1 to bbsy and 0 to scp. write transmit data in icdrt write 0 to bbsy and scp set mst to 1 and trs to 0 in iccr1 read bbsy in iccr2 read tend in icsr read ackbr in icier mater receive mode yes ackbr=0 ? write transmit data in icdrt read tdre in icsr read tend in icsr clear tend in icsr read stop in icsr clear tdre in icsr end write transmit data in icdrt transmit mode? no yes tdre=1 ? last byte? stop=1 ? no no no no no yes yes tend=1 ? yes yes yes [1] test the status of the scl and sda lines. [2] set master transmit mode. [3] issue the start candition. [4] set the first byte (slave address + r/ w ) of transmit data. [5] wait for 1 byte to be transmitted. [6] test the acknowledge transferred from the specified slave device. [7] set the second and subsequent bytes (except for the final byte) of transmit data. [8] wait for icdrt empty. [9] set the last byte of transmit data. [10] wait for last byte to be transmitted. [11] clear the tend flag. [12] clear the stop flag. [13] issue the stop condition. [14] wait for the creation of stop condition. [15] set slave receive mode. clear tdre. [12] clear stop in icsr figure 17.17 sample flowch art for master transmit mode section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 338 of 472 rej09b0160-0200 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? mater receive mode clear tend in icsr clear trs in iccr1 to 0 clear tdre in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 set rcvd in iccr1 to 1 read icdrr read rdrf in icsr write 0 to bbsy and scp read stop in icsr read icdrr clear rcvd in iccr1 to 0 clear mst in iccr1 to 0 note: do not activate an interrupt during the execution of steps [1] to [3]. supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. end no yes stop=1 ? no yes [1] clear tend, select master receive mode, and then clear tdre. * [2] set acknowledge to the transmit device. * [3] dummy-read icddr. * [4] wait for 1 byte to be received [5] check whether it is the (last receive - 1). [6] read the receive data last. [7] set acknowledge of the final byte. disable continuous reception (rcvd = 1). [8] read the (final byte - 1) of receive data. [9] wait for the last byte to be receive. [10] clear the stop flag. [11] issue the stop condition. [12] wait for the creation of stop condition. [13] read the last byte of receive data. [14] clear rcvd. [15] set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] clear stop in icsr. [10] [14] [15] figure 17.18 sample flowch art for master receive mode section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 339 of 472 rej09b0160-0200 tdre=1 ? yes yes no slave transmit mode clear aas in icsr write transmit data in icdrt read tdre in icsr last byte? write transmit data in icdrt read tend in icsr clear tend in icsr clear trs in iccr1 to 0 dummy read icdrr clear tdre in icsr end [1] clear the aas flag. [2] set transmit data for icdrt (except for the last data). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte to be transmitted. [6] clear the tend flag . [7] set slave receive mode. [8] dummy-read icdrr to release the scl line. [9] clear the tdre flag. no no yes tend=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] figure 17.19 sample flowchart for slave transmit mode section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 340 of 472 rej09b0160-0200 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? slave receive mode clear aas in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 read icdrr read rdrf in icsr read icdrr end no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. [2] set acknowledge to the transmit device. [3] dummy-read icdrr. [4] wait for 1 byte to be received. [5] check whether it is the (last receive - 1). [6] read the receive data. [7] set acknowledge of the last byte. [8] read the (last byte - 1) of receive data. [9] wait the last byte to be received. [10] read for the last byte of receive data. supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. figure 17.20 sample flowch art for slave receive mode section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 341 of 472 rej09b0160-0200 17.5 interrupt request there are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, nack receive, stop recogn ition, and arbitration lost/overrun error. table 17.3 shows the contents of each interrupt request. table 17.3 interrupt requests interrupt request abbreviat ion interrupt condition i 2 c mode clocked synchronous mode transmit data empty txi (tdre=1) ? (tie=1) { { transmit end tei (tend=1) ? (teie=1) { { receive data full rxi (rdrf=1) ? (rie=1) { { stop recognition stpi (stop=1) ? (stie=1) { nack receive { arbitration lost/overrun error naki {(nackf=1)+(al=1)} ? (nakie=1) { { when interrupt conditions described in table 17.3 are 1 and the i bit in ccr is 0, the cpu executes an interrupt exception pr ocessing. interrupt sources should be cleared in the exception processing. tdre and tend are automatically cl eared to 0 by writing the transmit data to icdrt. rdrf are automatically cl eared to 0 by readin g icdrr. tdre is set to 1 again at the same time when transmit data is written to icdrt. when tdre is cleared to 0, then an excessive data of one byte may be transmitted. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 342 of 472 rej09b0160-0200 17.6 bit synchronous circuit in master mode, this module has a possibility that high level period may be short in the two states described below. ? when scl is driven to low by the slave device ? when the rising speed of scl is lowered by the load of the scl line (load capacitance or pull- up resistance) therefore, it monitors scl and communicates by bit with synchronization. figure 17.21 shows the timing of the bit synchronous circuit and table 17.4 shows the time when scl output changes from low to hi-z then scl is monitored. scl vih scl monitor timing reference clock internal scl figure 17.21 the timing of the bit synchronous circuit table 17.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 343 of 472 rej09b0160-0200 17.7 usage notes 17.7.1 issue (retransmission) of start/stop conditions in master mode, when the start/stop conditions ar e issued (retransmitted) at the specific timing under the following condition 1 or 2, such cond itions may not be output successfully. to avoid this, issue (retransmit) the start/ stop conditions after the fall of th e ninth clock is confirmed. check the sclo bit in the i 2 c control register 2 (iicr2) to confirm the fall of the ninth clock. 1. when the rising of scl falls behind the time specified in section 17.6, bit synchronous circuit, by the load of the scl bus (l oad capacitance or pull-up resistance) 2. when the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 17.7.2 wait setting in i 2 c bus mode register (icmr) if the wait bit is set to 1, and the scl signal is dr iven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. to avoid this, set the wait bit in icmr to 0. section 17 i 2 c bus interface 2 (iic2) rev. 2.00 sep. 23, 2005 page 344 of 472 rej09b0160-0200 section 18 a/d converter adcms32a_000020020200 rev. 2.00 sep. 23, 2005 page 345 of 472 rej09b0160-0200 section 18 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. the block diagram of the a/d converter is shown in figure 18.1. 18.1 features ? 10-bit resolution ? eight input channels ? conversion time: at least 3.9 s per channel (at 18-mhz operation) ? two operating modes ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a data register for each channel ? sample-and-hold function ? two conversion start methods ? software ? external trigger signal ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated section 18 a/d converter rev. 2.00 sep. 23, 2005 page 346 of 472 rej09b0160-0200 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface successive approximations register analog multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a an0 an1 an2 an3 an4 an5 an6 an7 a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d [legend] adcr: adcsr: addra: addrb: addrc: addrd: adtrg ?/4 ?/8 av cc figure 18.1 block di agram of a/d converter section 18 a/d converter rev. 2.00 sep. 23, 2005 page 347 of 472 rej09b0160-0200 18.2 input/output pins table 18.1 summarizes the input pins used by th e a/d converter. the 8 analog input pins are divided into two groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1. the avcc pin is the power supply pin for the analog block in the a/d converter. table 18.1 pin configuration pin name abbreviation i/o function analog power supply pin av cc input analog block power supply analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion section 18 a/d converter rev. 2.00 sep. 23, 2005 page 348 of 472 rej09b0160-0200 18.3 register descriptions the a/d converter has the following registers. ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) ? a/d control register (adcr) 18.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which st ore a conversion result for each analog input channel, are shown in table 18.2. the converted 10-bit data is stored in bits 15 to 6. the lower 6 bits are always read as 0. the data bus width between the cpu and the a/d converter is 8 bits. the upper byte can be read directly from the cpu, however the lower byte should be r ead via a temporary register. the temporary register cont ents are transferred from the addr when the upper byte data is read. therefore byte access to add r should be done by r eading the upper byte first then the lower one. word access is also possible. ad dr is initialized to h'0000. table 18.2 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register to be stored results of a/d conversion an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd section 18 a/d converter rev. 2.00 sep. 23, 2005 page 349 of 472 rej09b0160-0200 18.3.2 a/d control/status register (adcsr) adcsr consists of the control bits and conversion end status bits of the a/d converter. bit bit name initial value r/w description 7 adf 0 r/w a/d end flag [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends once on all the channels selected in scan mode [clearing condition] ? when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt request (adi) is enabled by adf when this bit is set to 1 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 cks 0 r/w clock select selects the a/d conversions time. 0: conversion time = 134 states (max.) 1: conversion time = 70 states (max.) clear the adst bit to 0 before switching the conversion time. section 18 a/d converter rev. 2.00 sep. 23, 2005 page 350 of 472 rej09b0160-0200 bit bit name initial value r/w description 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 2 to 0 select analog input channels. when scan = 0 when scan = 1 000: an0 000: an0 001: an1 001: an0 and an1 010: an2 010: an0 to an2 011: an3 011: an0 to an3 100: an4 100: an4 101: an5 101: an4 and an5 110: an6 110: an4 to an6 111: an7 111: an4 to an7 18.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 trge 0 r/w trigger enable a/d conversion is started at the falling edge and the rising edge of the external trigger signal ( adtrg ) when this bit is set to 1. the selection between the falling edge and rising edge of the external trigger pin ( adtrg ) conforms to the wpeg5 bit in the interrupt edge select register 2 (iegr2) 6 to 1 ? all 1 ? reserved these bits are always read as 1. 0 ? 0 r/w reserved do not set this bit to 1, though the bit is readable/writable. section 18 a/d converter rev. 2.00 sep. 23, 2005 page 351 of 472 rej09b0160-0200 18.4 operation the a/d converter operates by su ccessive approximation with 10-b it resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent in correct operation, first clear th e bit adst in adcsr to 0. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 18.4.1 single mode in single mode, a/d conversion is performed once for the analog input of the specified single channel as follows: 1. a/d conversion is started when the adst bit in adcsr is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the resu lt is transferred to the corresponding a/d data register of the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 18.4.2 scan mode in scan mode, a/d conversion is performed sequentially for the analog input of the specified channels (four channels maximum) as follows: 1. when the adst bit in adcsr is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1). 2. when a/d conversion for each channel is comple ted, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt requested is generated. a/d conversion starts again on the first channel in the group. 4. the adst bit is not automatically cleared to 0. steps [2] and [3] are re peated as long as the adst bit remains set to 1. when the adst bi t is cleared to 0, a/ d conversion stops. section 18 a/d converter rev. 2.00 sep. 23, 2005 page 352 of 472 rej09b0160-0200 18.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 18.2 shows the a/d conversion timing. table 18.3 shows the a/d conversion time. as indicated in figure 18.2, th e a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the wr ite access to adcsr. the total conversion time therefore varies w ithin the ranges indicated in table 18.3. in scan mode, the values given in table 18.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 128 states (fixed) when cks = 0 and 66 states (fixed) when cks = 1. (1) (2) t d t spl t conv address write signal input sampling timing adf [legend] (1) : (2) : t d : t spl : t conv : adcsr write cycle adcsr address a/d conversion start delay time input sampling time a/d conversion time figure 18.2 a/d conversion timing section 18 a/d converter rev. 2.00 sep. 23, 2005 page 353 of 472 rej09b0160-0200 table 18.3 a/d conversio n time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay time t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: all values represent the number of states. 18.4.4 external tr igger input timing a/d conversion can also be started by an external trigger input. when the trge bit in adcr is set to 1, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg input pin sets the adst bit in adcsr to 1, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 18.3 shows the timing. internal trigger signal adst a/d conversion figure 18.3 external trigger input timing section 18 a/d converter rev. 2.00 sep. 23, 2005 page 354 of 472 rej09b0160-0200 18.5 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 18.4). ? offset error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 18.5). ? full-scale error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 18.5). ? nonlinearity error the deviation from the ideal a/d conversion charact eristic as the voltage changes from zero to full scale. this does not include the offset error, full-scale error, or quantization error. ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error. section 18 a/d converter rev. 2.00 sep. 23, 2005 page 355 of 472 rej09b0160-0200 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 18.4 a/d conversio n accuracy definitions (1) fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 18.5 a/d conversio n accuracy definitions (2) section 18 a/d converter rev. 2.00 sep. 23, 2005 page 356 of 472 rej09b0160-0200 18.6 usage notes 18.6.1 permissible si gnal source impedance this lsi's analog input is designed such that conv ersion accuracy is guarant eed for an input signal for which the signal source impedance is 5 k ? or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversi on accuracy. however, for a/d co nversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 18.6). when converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 18.6.2 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefor e noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. 20 pf 10 k ? c in = 15 pf sensor output impedance up to 5 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 18.6 analog input circuit example section 19 list of registers rev. 2.00 sep. 23, 2005 page 357 of 472 rej09b0160-0200 section 19 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? the symbol ? in the register-name column represents a reserved address or range of reserved addresses. do not attempt to access reserved addresses. ? when the address is 16-bit wide, the address of the upper byte is given in the list. ? registers are classified by functional modules. ? the data bus width is indicated. ? the number of access states is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? when registers consist of 16 bits, bits are described from the msb side. 3. register states in each operating mode ? register states are described in the sa me order as the register addresses. ? the register states described here are for the basic operating mode s. if there is a specific reset for an on-chip peripheral module, refer to th e section on that on-chip peripheral module. section 19 list of registers rev. 2.00 sep. 23, 2005 page 358 of 472 rej09b0160-0200 19.1 register addresses (address order) the data-bus width column indicates the numb er of bits. the access-st ate column shows the number of states of the sel ected basic clock that is requi red for access to the register. note: access to undefined or reserved addresses should not take place. co rrect operation of the access itself or later operations is not guara nteed when such a register is accessed. register abbre- viation bit no address module name data bus width access state ? ? ? h'f000 to h'f6ff ? ? ? timer control register_0 tcr_0 8 h'f700 timer z 8 2 timer i/o control register a_0 tiora_0 8 h'f701 timer z 8 2 timer i/o control register c_0 tiorc_0 8 h'f702 timer z 8 2 timer status register_0 tsr_0 8 h'f703 timer z 8 2 timer interrupt enable register_0 tier_0 8 h'f704 timer z 8 2 pwm mode output level control register_0 pocr_0 8 h'f705 timer z 8 2 timer counter_0 tcnt_0 16 h'f706 timer z 16 2 general register a_0 gra_0 16 h'f708 timer z 16 2 general register b_0 grb_0 16 h'f70a timer z 16 2 general register c_0 grc_0 16 h'f70c timer z 16 2 general register d_0 grd_0 16 h'f70e timer z 16 2 timer control register_1 tcr_1 8 h'f710 timer z 8 2 timer i/o control register a_1 tiora_1 8 h'f711 timer z 8 2 timer i/o control register c_1 tiorc_1 8 h'f712 timer z 8 2 timer status register_1 tsr_1 8 h'f713 timer z 8 2 timer interrupt enable register_1 tier_1 8 h'f714 timer z 8 2 pwm mode output level control register_1 pocr_1 8 h'f715 timer z 8 2 timer counter_1 tcnt_1 16 h'f716 timer z 16 2 section 19 list of registers rev. 2.00 sep. 23, 2005 page 359 of 472 rej09b0160-0200 register abbre- viation bit no address module name data bus width access state general register a_1 gra_1 16 h'f718 timer z 16 2 general register b_1 grb_1 16 h'f71a timer z 16 2 general register c_1 grc_1 16 h'f71c timer z 16 2 general register d_1 grd_1 16 h'f71e timer z 16 2 timer start register tstr 8 h'f720 timer z 8 2 timer mode register tmdr 8 h'f721 timer z 8 2 timer pwm mode register tpmr 8 h'f722 timer z 8 2 timer z, for common use tfcr 8 h'f723 timer z 8 2 timer output master enable register toer 8 h'f724 timer z 8 2 timer output control register tocr 8 h'f725 timer z 8 2 ? ? ? h'f726, h'f727 ? ? ? second data register/free running counter data register rsecdr 8 h'f728 rtc 8 2 minute data register rmindr 8 h'f729 rtc 8 2 hour data register rhrdr 8 h'f72a rtc 8 2 day-of-week data register rwkdr 8 h'f72b rtc 8 2 rtc control register 1 rtccr1 8 h'f72c rtc 8 2 rtc control register 2 rtccr2 8 h'f72d rtc 8 2 ? ? ? h'f72e rtc ? ? clock source select register rtccsr 8 h'f72f rtc 8 2 ? ? ? h'f730 to h'f73f ? ? ? serial mode register_2 smr_2 8 h'f740 sci3_2 8 3 bit rate register_2 brr_2 8 h'f741 sci3_2 8 3 serial control register 3_2 scr3_2 8 h'f742 sci3_2 8 3 transmit data register_2 t dr_2 8 h'f743 sci3_2 8 3 serial status register_2 ssr_2 8 h'f744 sci3_2 8 3 receive data register_2 rdr_2 8 h'f745 sci3_2 8 3 ? ? ? h'f746, h'f747 ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 360 of 472 rej09b0160-0200 register abbre- viation bit no address module name data bus width access state i2c bus control register 1 iccr1 8 h'f748 iic2 8 2 i2c bus control register 2 iccr2 8 h'f749 iic2 8 2 i2c bus mode register icmr 8 h'f74a iic2 8 2 i2c bus interrupt enable register icier 8 h'f74b iic2 8 2 i2c status register icsr 8 h'f74c iic2 8 2 slave address register sar 8 h'f74d iic2 8 2 i2c bus transmit data register icdrt 8 h'f74e iic2 8 2 i2c bus receive data register icdrr 8 h'f74f iic2 8 2 ? ? ? h'f750 to h'f75f ? ? ? timer mode register b1 tmb1 8 h'f760 timer b1 8 2 timer counter b1 tcb1 8 h'f761 timer b1 8 2 timer load register b1 tlb1 8 h'f761 timer b1 8 2 ? ? ? h'f762 to h'ff8f ? ? ? flash memory control register 1 flmcr1 8 h'ff90 rom 8 2 flash memory control register 2 flmcr2 8 h'ff91 rom 8 2 flash memory power control register flpwcr 8 h'ff92 rom 8 2 erase block register 1 ebr1 8 h'ff93 rom 8 2 ? ? ? h'ff94 to h'ff9a ? ? ? flash memory enable regist er fenr 8 h'ff9b rom 8 2 ? ? ? h'ff9c to h'ff9f ? ? ? timer control register v0 tcrv0 8 h'ffa0 timer v 8 3 timer control/status register v tcsrv 8 h'ffa1 timer v 8 3 time constant register a tcora 8 h'ffa2 timer v 8 3 time constant register b tcorb 8 h'ffa3 timer v 8 3 timer counter v tcntv 8 h'ffa4 timer v 8 3 timer control register v1 tcrv1 8 h'ffa5 timer v 8 3 ? ? ? h'ffa6, h'ffa7 ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 361 of 472 rej09b0160-0200 register abbre- viation bit no address module name data bus width access state serial mode register smr 8 h'ffa8 sci3 8 3 bit rate register brr 8 h'ffa9 sci3 8 3 serial control register 3 scr3 8 h'ffaa sci3 8 3 transmit data register tdr 8 h'ffab sci3 8 3 serial status register ssr 8 h'ffac sci3 8 3 receive data register rdr 8 h'ffad sci3 8 3 ? ? ? h'ffae, h'ffaf ? ? ? a/d data register addra 16 h'ffb0 a/d converter 8 3 a/d data register addrb 16 h'ffb2 a/d converter 8 3 a/d data register addrc 16 h'ffb4 a/d converter 8 3 a/d data register addrd 16 h'ffb6 a/d converter 8 3 a/d control/status register a dcsr 8 h'ffb8 a/d converter 8 3 a/d control register adcr 8 h'ffb9 a/d converter 8 3 ? ? ? h'ffba, h'ffbb ? ? ? pwm data register l pwdrl 8 h'ffbc 14-bit pwm 8 2 pwm data register u pwdru 8 h'ffbd 14-bit pwm 8 2 pwm control register pwcr 8 h'ffbe 14-bit pwm 8 2 ? ? ? h'ffbf 14-bit pwm ? ? timer control/status register wd tcsrwd 8 h'ffc0 wdt * 8 2 timer counter wd tcwd 8 h'ffc1 wdt * 8 2 timer mode register wd tmwd 8 h'ffc2 wdt * 8 2 ? ? ? h'ffc3 wdt * ? ? ? ? ? h'ffc4 to h'ffc7 ? ? ? address break control re gister abrkcr 8 h'ffc8 address break 8 2 address break status r egister abrksr 8 h'ffc9 address break 8 2 break address register h barh 8 h'ffca address break 8 2 break address register l barl 8 h'ffcb address break 8 2 break data register h bdrh 8 h'ffcc address break 8 2 section 19 list of registers rev. 2.00 sep. 23, 2005 page 362 of 472 rej09b0160-0200 register abbre- viation bit no address module name data bus width access state break data register l bdrl 8 h'ffcd address break 8 2 port pull-up control register 1 pucr1 8 h'ffd0 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffd1 i/o port 8 2 ? ? ? h'ffd2, h'ffd3 ? ? ? port data register 1 pdr1 8 h'ffd4 i/o port 8 2 port data register 2 pdr2 8 h'ffd5 i/o port 8 2 port data register 3 pdr3 8 h'ffd6 i/o port 8 2 ? ? ? h'ffd7 i/o port ? ? port data register 5 pdr5 8 h'ffd8 i/o port 8 2 port data register 6 pdr6 8 h'ffd9 i/o port 8 2 port data register 7 pdr7 8 h'ffda i/o port 8 2 port data register 8 pdr8 8 h'ffdb i/o port 8 2 ? ? ? h'ffdc i/o port ? ? port data register b pdrb 8 h'ffdd i/o port 8 2 ? ? ? h'ffde, h'ffdf ? ? ? port mode register 1 pmr1 8 h'ffe0 i/o port 8 2 port mode register 5 pmr5 8 h'ffe1 i/o port 8 2 port mode register 3 pmr3 8 h'ffe2 i/o port 8 2 ? ? ? h'ffd3 i/o port ? ? port control register 1 pcr1 8 h'ffe4 i/o port 8 2 port control register 2 pcr2 8 h'ffe5 i/o port 8 2 port control register 3 pcr3 8 h'ffe6 i/o port 8 2 ? ? ? h'ffe7 i/o port ? ? port control register 5 pcr5 8 h'ffe8 i/o port 8 2 port control register 6 pcr6 8 h'ffe9 i/o port 8 2 port control register 7 pcr7 8 h'ffea i/o port 8 2 port control register 8 pcr8 8 h'ffeb i/o port 8 2 ? ? ? h'ffec to h'ffef ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 363 of 472 rej09b0160-0200 register abbre- viation bit no address module name data bus width access state system control register 1 syscr1 8 h'fff0 low power 8 2 system control register 2 syscr2 8 h'fff1 low power 8 2 interrupt edge select register 1 iegr1 8 h'fff2 interrupt 8 2 interrupt edge select register 2 iegr2 8 h'fff3 interrupt 8 2 interrupt enable register 1 ienr1 8 h'fff4 interrupt 8 2 interrupt enable register 2 ienr2 8 h'fff5 interrupt 8 2 interrupt flag register 1 irr1 8 h'fff6 interrupt 8 2 interrupt flag register 2 irr2 8 h'fff7 interrupt 8 2 wakeup interrupt flag register iwpr 8 h'fff8 interrupt 8 2 module standby control register 1 mstcr1 8 h'fff9 low power 8 2 module standby control register 2 mstcr2 8 h'fffa low power 8 2 ? ? ? h'fffb to h'ffff ? ? ? note: * wdt: watchdog timer section 19 list of registers rev. 2.00 sep. 23, 2005 page 364 of 472 rej09b0160-0200 19.2 register bits the addresses and bit names of the registers in the on-chip peripheral modules are listed below. the 16-bit register is indicated in two rows, 8 bits for each row. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ? ? ? ? ? ? ? ? ? ? tcr_0 cclr2 cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 timer z tiora_0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tiorc_0 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tsr_0 ? ? ? ovf imfd imfc imfb imfa tier_0 ? ? ? ovie imied imiec imieb imiea pocr_0 ? ? ? ? ? pold polc polb tcnt_0 tcnt0h7 tcnt0h6 tcnt0h5 tcnt0h 4 tcnt0h3 tcnt0h2 tcnt0h1 tcnt0h0 tcnt0l7 tcnt0l6 tcnt0l5 tcnt0l4 tcnt0l3 tcnt0l2 tcnt0l1 tcnt0l0 gra_0 gra0h7 gra0h6 gra0h5 gra0h4 gra0h3 gra0h2 gra0h1 gra0h0 gra0l7 gra0l6 gra0l5 gra0l4 gra0l3 gra0l2 gra0l1 gra0l0 grb_0 grb0h7 grb0h6 grb0h5 grb0h4 grb0h3 grb0h2 grb0h1 grb0h0 grb0l7 grb0l6 grb0l5 grb0l4 grb0l3 grb0l2 grb0l1 grb0l0 grc_0 grc0h7 grc0h6 grc0h5 grc0h4 grc0h3 grc0h2 grc0h1 grc0h0 grc0l7 grc0l6 grc0l5 grc0l4 grc0l3 grc0l2 grc0l1 grc0l0 grd_0 grd0h7 grd0h6 grd0h5 grd0h4 grd0h3 grd0h2 grd0h1 grd0h0 grd0l7 grd0l6 grd0l5 grd0l4 grd0l3 grd0l2 grd0l1 grd0l0 tcr_1 cclr2 cclr1 cclr0 ckeg 1 ckeg0 tpsc2 tpsc1 tpsc0 tiora_1 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tiorc_1 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tsr_1 ? ? udf ovf imfd imfc imfb imfa tier_1 ? ? ? ovie imied imiec imieb imiea pocr_1 ? ? ? ? ? pold polc polb tcnt_1 tcnt1h7 tcnt1h6 tcnt1h5 tcnt1h 4 tcnt1h3 tcnt1h2 tcnt1h1 tcnt1h0 tcnt1l7 tcnt1l6 tcnt1l5 tcnt1l4 tcnt1l3 tcnt1l2 tcnt1l1 tcnt1l0 gra_1 gra1h7 gra1h6 gra1h5 gra1h4 gra1h3 gra1h2 gra1h1 gra1h0 gra1l7 gra1l6 gra1l5 gra1l4 gra1l3 gra1l2 gra1l1 gra1l0 section 19 list of registers rev. 2.00 sep. 23, 2005 page 365 of 472 rej09b0160-0200 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name grb_1 grb1h7 grb1h6 grb1h5 grb1h4 gr b1h3 grb1h2 grb1h1 grb1h0 timer z grb1l7 grb1l6 grb1l5 grb1l4 gr b1l3 grb1l2 grb1l1 grb1l0 grc_1 grc1h7 grc1h6 grc1h5 grc1h4 grc1h3 grc1h2 grc1h1 grc1h0 grc1l7 grc1l6 grc1l5 grc1l4 grc1l3 grc1l2 grc1l1 grc1l0 grd_1 grd1h7 grd1h6 grd1h5 grd1h4 grd1h3 grd1h2 grd1h1 grd1h0 grd1l7 grd1l6 grd1l5 grd1l4 grd1l3 grd1l2 grd1l1 grd1l0 tstr ? ? ? ? ? ? str1 str0 tmdr bfd1 bfc1 bfd0 bfc0 ? ? ? sync tpmr ? pwmd1 pwmc1 pwmb1 ? pwmd0 pwmc0 pwmb0 tfcr ? stclk adeg adtrg ols1 ols0 cmd1 cmd0 toer ed1 ec1 eb1 ea1 ed0 ec0 eb0 ea0 tocr tod1 toc1 tob1 toa1 tod0 toc0 tob0 toa0 rsecdr bsy sc12 sc11 sc10 sc03 sc02 sc01 sc00 rtc rmindr bsy mn12 mn11 mn10 mn03 mn02 mn01 mn00 rhrdr bsy ? hr11 hr10 hr03 hr02 hr01 hr00 rwkdr bsy ? ? ? ? wk2 wk1 wk0 rtccr1 run 12/24 pm rst ? ? ? ? rtccr2 ? ? foie wkie dyie hrie mnie seie rtccsr ? rcs6 rcs5 ? rcs3 rcs2 rcs1 rcs0 ? ? ? ? ? ? ? ? ? ? smr_2 com chr pe pm stop mp cks1 cks0 sci3_2 brr_2 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3_2 tie rie te re mpie teie cke1 cke0 tdr_2 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr_2 tdre rdrf oer fer per tend mpbr mpbt rdr_2 rdr7 rdr6 rdr5 rdr4 rd r3 rdr2 rdr1 rdr0 iccr1 ice rcvd mst trs cks3 cks2 cks1 cks0 iic2 iccr2 bbsy scp sdao sdaop sclo ? iicrst ? icmr mls wait ? ? bcwp bc2 bc1 bc0 icier tie teie rie nakie stie acke ackbr ackbt icsr tdre tend rdrf nackf stop al/ove aas adz section 19 list of registers rev. 2.00 sep. 23, 2005 page 366 of 472 rej09b0160-0200 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs iic2 icdrt icdrt7 icdrt6 icdrt5 icdrt4 icdrt3 icdrt2 icdrt1 icdrt0 icdrr icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 ? ? ? ? ? ? ? ? ? ? tmb1 tmb17 ? ? ? ? tmb12 tmb11 tmb10 timer b1 tcb1 tcb17 tcb16 tcb15 tcb 14 tcb13 tcb12 tcb11 tcb10 tlb1 tlb17 tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 ? ? ? ? ? ? ? ? ? ? flmcr1 ? swe esu psu ev pv e p rom flmcr2 fler ? ? ? ? ? ? ? flpwcr pdwnd ? ? ? ? ? ? ? ebr1 ? eb6 eb5 eb4 eb3 eb2 eb1 eb0 fenr flshe ? ? ? ? ? ? ? tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v tcsrv cmfb cmfa ovf ? os3 os2 os1 os0 tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 tcrv1 ? ? ? tveg1 tveg0 trge ? icks0 ? ? ? ? ? ? ? ? ? ? smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf oer fer per tend mpbr mpbt rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 addra ad9 ad8 ad7 ad 6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? a/d converter addrb ad9 ad8 ad7 ad 6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 367 of 472 rej09b0160-0200 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name addrc ad9 ad8 ad7 ad6 ad5 ad 4 ad3 ad2 a/d converter ad1 ad0 ? ? ? ? ? ? addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst sc an cks ch2 ch1 ch0 adcr trge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pwdrl pwdrl7 pwdrl6 pwdrl5 pwdrl4 pwdr l3 pwdrl2 pwdrl1 pwdrl0 14-bit pwm pwdru ? ? pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 pwcr ? ? ? ? ? ? ? pwcr0 tcsrwd b6wi tcwe b4wi tcsrwe b2wi wdon b0wi wrst wdt * tcwd tcwd7 tcwd6 tcwd5 tcwd 4 tcwd3 tcwd2 tcwd1 tcwd0 tmwd ? ? ? ? cks3 cks2 cks1 cks0 ? ? ? ? ? ? ? ? ? ? abrkcr rtinte csel1 csel0 ac mp2 acmp1 acmp0 dcmp1 dcmp0 abrksr abif abie ? ? ? ? ? ? address break barh barh7 barh6 barh5 barh4 barh3 barh2 barh1 barh0 barl barl7 barl6 barl5 barl4 barl3 barl2 barl1 barl0 bdrh bdrh7 bdrh6 bdrh5 bdrh4 bdrh3 bdrh2 bdrh1 bdrh0 bdrl bdrl7 bdrl6 bdrl5 bdr l4 bdrl3 bdrl2 bdrl1 bdrl0 ? ? ? ? ? ? ? ? ? ? pucr1 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 i/o port pucr5 ? ? pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 pdr1 p17 p16 p15 p14 ? p12 p11 p10 pdr2 ? ? ? p24 p23 p22 p21 p20 pdr3 p37 p36 p35 p34 p33 p32 p31 p30 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 pdr7 ? p76 p75 p74 ? p72 p71 p70 pdr8 p87 p86 p85 ? ? ? ? ? pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 section 19 list of registers rev. 2.00 sep. 23, 2005 page 368 of 472 rej09b0160-0200 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pmr1 irq3 irq2 irq1 irq0 txd2 pwm txd tmow i/o port pmr5 pof57 pof56 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pmr3 ? ? ? pof24 pof23 ? ? ? pcr1 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 pcr2 ? ? ? pcr24 pcr23 pcr22 pcr21 pcr20 pcr3 pcr37 pcr36 pcr35 pcr 34 pcr33 pcr32 pcr31 pcr30 pcr5 pcr57 * 3 pcr56 * 3 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 pcr6 pcr67 pcr66 pcr65 pcr 64 pcr63 pcr62 pcr61 pcr60 pcr7 ? pcr76 pcr75 pcr74 ? pcr72 pcr71 pcr70 pcr8 pcr87 pcr86 pcr85 ? ? ? ? ? syscr1 ssby sts2 sts1 sts0 nesel ? ? ? low power syscr2 smsel lson dton ma2 ma1 ma0 sa1 sa0 iegr1 nmieg ? ? ? ieg3 ieg2 ieg1 ieg0 interrupt iegr2 ? ? wpeg5 wpeg4 wpeg3 wpeg2 wpeg1 wpeg0 ienr1 iendt ienta ienwp ? ien3 ien2 ien1 ien0 ienr2 ? ? ientb1 ? ? ? ? ? irr1 irrdt irrta ? ? irri3 irri2 irri1 irri0 irr2 ? ? irrtb1 ? ? ? ? ? iwpr ? ? iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 interrupt mstcr1 ? mstiic msts3 mstad mstwd ? msttv mstta low power mstcr2 msts3_2 ? ? msttb1 ? ? msttz mstpwm ? ? ? ? ? ? ? ? ? ? note: * wdt: watchdog timer section 19 list of registers rev. 2.00 sep. 23, 2005 page 369 of 472 rej09b0160-0200 19.3 registers states in each operating mode register name reset active sleep subactive subsleep standby module tcr_0 initialized ? ? ? ? ? timer z tiora_0 initialized ? ? ? ? ? tiorc_0 initialized ? ? ? ? ? tsr_0 initialized ? ? ? ? ? tier_0 initialized ? ? ? ? ? pocr_0 initialized ? ? ? ? ? tcnt_0 initialized ? ? ? ? ? gra_0 initialized ? ? ? ? ? grb_0 initialized ? ? ? ? ? grc_0 initialized ? ? ? ? ? grd_0 initialized ? ? ? ? ? tcr_1 initialized ? ? ? ? ? tiora_1 initialized ? ? ? ? ? tiorc_1 initialized ? ? ? ? ? tsr_1 initialized ? ? ? ? ? tier_1 initialized ? ? ? ? ? pocr_1 initialized ? ? ? ? ? tcnt_1 initialized ? ? ? ? ? gra_1 initialized ? ? ? ? ? grb_1 initialized ? ? ? ? ? grc_1 initialized ? ? ? ? ? grd_1 initialized ? ? ? ? ? tstr initialized ? ? ? ? ? tmdr initialized ? ? ? ? ? tpmr initialized ? ? ? ? ? tfcr initialized ? ? ? ? ? toer initialized ? ? ? ? ? tocr initialized ? ? ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 370 of 472 rej09b0160-0200 register name reset active sleep subactive subsleep standby module rsecdr ? ? ? ? ? ? rtc rmindr ? ? ? ? ? ? rhrdr ? ? ? ? ? ? rwkdr ? ? ? ? ? ? rtccr1 ? ? ? ? ? ? rtccr2 ? ? ? ? ? ? rtccsr initialized ? ? ? ? ? smr_2 initialized ? ? initialized initializ ed initialized sci3_2 brr_2 initialized ? ? initialized initialized initialized scr3_2 initialized ? ? initialized initialized initialized tdr_2 initialized ? ? initialized initialized initialized ssr_2 initialized ? ? initialized initialized initialized rdr_2 initialized ? ? initialized initialized initialized iccr1 initialized ? ? ? ? ? iic2 iccr2 initialized ? ? ? ? ? icmr initialized ? ? ? ? ? icier initialized ? ? ? ? ? icsr initialized ? ? ? ? ? sar initialized ? ? ? ? ? icdrt initialized ? ? ? ? ? icdrr initialized ? ? ? ? ? tmb1 initialized ? ? ? ? ? timer b1 tcb1 initialized ? ? ? ? ? tlb1 initialized ? ? ? ? ? flmcr1 initialized ? ? initialized initialized initialized rom flmcr2 initialized ? ? ? ? ? flpwcr initialized ? ? ? ? ? ebr1 initialized ? ? initialized initialized initialized fenr initialized ? ? ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 371 of 472 rej09b0160-0200 register name reset active sleep subactive subsleep standby module tcrv0 initialized ? ? initialized initialized initialized timer v tcsrv initialized ? ? initialized initialized initialized tcora initialized ? ? initialized initialized initialized tcorb initialized ? ? initialized initialized initialized tcntv initialized ? ? initialized initialized initialized tcrv1 initialized ? ? initialized initialized initialized smr initialized ? ? initialized initializ ed initialized sci3 brr initialized ? ? initialized initialized initialized scr3 initialized ? ? initialized initialized initialized tdr initialized ? ? initialized initialized initialized ssr initialized ? ? initialized initialized initialized rdr initialized ? ? initialized initialized initialized addra initialized ? ? initialized initialized initialized a/d converter addrb initialized ? ? initialized initialized initialized addrc initialized ? ? initialized initialized initialized addrd initialized ? ? initialized initialized initialized adcsr initialized ? ? initialized initialized initialized adcr initialized ? ? initialized initialized initialized pwdrl initialized ? ? ? ? ? 14bit pwm pwdru initialized ? ? ? ? ? pwcr initialized ? ? ? ? ? tcsrwd initialized ? ? ? ? ? wdt * tcwd initialized ? ? ? ? ? tmwd initialized ? ? ? ? ? abrkcr initialized ? ? ? ? ? address break abrksr initialized ? ? ? ? ? barh initialized ? ? ? ? ? barl initialized ? ? ? ? ? bdrh initialized ? ? ? ? ? bdrl initialized ? ? ? ? ? section 19 list of registers rev. 2.00 sep. 23, 2005 page 372 of 472 rej09b0160-0200 register name reset active sleep subactive subsleep standby module pucr1 initialized ? ? ? ? ? i/o port pucr5 initialized ? ? ? ? ? pdr1 initialized ? ? ? ? ? pdr2 initialized ? ? ? ? ? pdr3 initialized ? ? ? ? ? pdr5 initialized ? ? ? ? ? pdr6 initialized ? ? ? ? ? pdr7 initialized ? ? ? ? ? pdr8 initialized ? ? ? ? ? pdrb initialized ? ? ? ? ? pmr1 initialized ? ? ? ? ? pmr5 initialized ? ? ? ? ? pmr3 initialized ? ? ? ? ? pcr1 initialized ? ? ? ? ? pcr2 initialized ? ? ? ? ? pcr3 initialized ? ? ? ? ? pcr5 initialized ? ? ? ? ? pcr6 initialized ? ? ? ? ? pcr7 initialized ? ? ? ? ? pcr8 initialized ? ? ? ? ? syscr1 initialized ? ? ? ? ? low power syscr2 initialized ? ? ? ? ? iegr1 initialized ? ? ? ? ? interrupt iegr2 initialized ? ? ? ? ? ienr1 initialized ? ? ? ? ? ienr2 initialized ? ? ? ? ? irr1 initialized ? ? ? ? ? irr2 initialized ? ? ? ? ? iwpr initialized ? ? ? ? ? mstcr1 initialized ? ? ? ? ? low power mstcr2 initialized ? ? ? ? ? note: * wdt: watchdog timer section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 373 of 472 rej09b0160-0200 section 20 electrical characteristics 20.1 absolute maximum ratings table 20.1 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +4.3 v * analog power supply voltage av cc ?0.3 to +4.3 v input voltage ports other than ports b and x1 v in ?0.3 to v cc +0.3 v port b ?0.3 to av cc +0.3 v x1 ?0.3 to 4.3 v operating temperature t opr ?20 to +75 c storage temperature t stg ?55 to +125 c note: * permanent damage may result if maximu m ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 20.2 electrical characteristics (f-ztat? version) 20.2.1 power supply voltage and operating ranges (1) power supply voltage and oscillation frequency range 4.0 18.0 3.0 3.6 vcc(v) osc (mhz) 32.768 3.0 3.6 vcc(v) w (khz) av cc = 3.0 to 3.6v active mode av cc = 3.0 to 3.6v all operating modes sleep mode section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 374 of 472 rej09b0160-0200 (2) power supply voltage and operating frequency range 16.384 8.192 4.096 3.0 3.6 vcc(v) w(khz) 4.0 18.0 3.0 3.6 vcc(v) osc(mhz) av cc = 3.0 to 3.6v 78.125 2250 3.0 3.6 vcc(v) (khz) av cc = 3.0 to 3.6v av cc = 3.0 to 3.6v active mode sleep mode (when ma2 is syscr2 = 1) active mode sleep mode (when ma2 is syscr2 = 0) subactive mode subsleep mode (3) analog power supply voltage and a/ d converter accuracy guarantee range 4.0 18.0 3.0 3.6 avcc(v) v cc = 3.0 to 3.6v osc(mhz) active mode sleep mode section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 375 of 472 rej09b0160-0200 20.2.2 dc characteristics table 20.2 dc characteristics (1) v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, v cc 0.8 ? v cc + 0.3 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1,sck3, sck3_2, trgv rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc 0.7 ? v cc + 0.3 v p50 to p57, p60 to p67, p70 to p72 p74 to p76, p85 to p87 pb0 to pb7 v cc 0.7 ? av cc + 0.3 v osc1 v cc ? 0.5 ? v cc + 0.3 v input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, ?0.3 ? v cc 0.2 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv note: connect the test pin to vss. section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 376 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?0.3 ? v cc 0.3 v p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87 pb0 to pb7 ?0.3 ? v cc 0.3 v osc1 ?0.3 ? 0.5 v output high voltage v oh p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?i oh = 2.0 ma v cc ? 0.5 ? ? v p50 to p55, p60 to p67, p70 to p72, p74 to p76, p85 to p87, p56, p57 ?i oh = 0.1 ma v cc ? 2.0 ? ? v output low voltage v ol p10 to p12, p14 to p17, p20 to p24, p30 to p37, i ol = 1.6 ma ? ? 0.6 v p50 to p57, p70 to p72, p74 to p76, p85 to p87 i ol = 0.4 ma ? ? 0.4 p60 to p67 i ol = 10.0 ma ? ? 1.0 v i ol = 1.6 ma ? ? 0.4 scl, sda i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4 section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 377 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes input/ output leakage current | i il | osc1, tmib1, nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1 rxd, sck3, rxd_2, sck3_2, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p24, p30 to p37, p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87, v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a pull-up mos current ?i p p10 to p12, p14 to p17, p50 to p55 v cc = 3.3 v, v in = 0.0 v 33.0 ? 165.0 a pull-up register r p res 60.0 150 ? k ? input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf i ope1 v cc active mode 1 v cc = 3.3 v, f osc = 18 mhz ? 21.0 28.0 ma * active mode current consump- tion active mode 1 v cc = 3.3 v, f osc = 10 mhz ? 11.6 ? * reference value i ope2 v cc active mode 2 v cc = 3.3 v, f osc = 18 mhz ? 1.4 2.8 ma * active mode 2 v cc = 3.3 v, f osc = 10 mhz ? 1.2 ? * reference value section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 378 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes i sleep1 v cc sleep mode 1 v cc = 3.3 v, f osc = 18 mhz ? 16.5 21.0 ma * sleep mode current consumpti on sleep mode 1 v cc = 3.3 v, f osc = 10 mhz ? 9.0 ? * reference value i sleep2 v cc sleep mode 2 v cc = 3.3 v, f osc = 18 mhz ? 1.3 2.5 ma * sleep mode 2 v cc = 3.3 v, f osc = 10 mhz ? 1.1 ? * reference value i sub v cc v cc = 3.3 v 32-khz crystal resonator ( sub = w /2) ? 35.0 60.0 a * subactive mode current consump- tion v cc = 3.3 v 32-khz crystal resonator ( sub = w /8) ? 20.0 ? * reference value subsleep mode current consump- tion i subsp1 v cc subsleep mode 1 v cc = 3.3 v 32-khz crystal resonator ( sub = w /2) ? 20.0 40.0 a * i subsp2 v cc subsleep mode 2 v cc = 3.3 v 32-khz crystal resonator not used ? ? 5.0 ? * standby mode current consump- tion i stby v cc 32-khz crystal resonator not used ? ? 5.0 a * ram data retaining voltage v ram v cc 2.0 ? ? v section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 379 of 472 rej09b0160-0200 note: * pin states during current consumption meas urement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator active mode 2 operates ( osc/64) subclock: pin x1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc/64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode 1 v cc only timers operate v cc subclock: crystal resonator subsleep mode 2 cpu and timers both stop main clock: ceramic or crystal resonator subclock: pin x1 = v ss standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x1 = v ss section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 380 of 472 rej09b0160-0200 table 20.2 dc characteristics (2) v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit allowable output low current (per pin) i ol output pins except port 6, scl, and sda ? ? 2.0 ma port 6 ? ? 10.0 scl, sda ? ? 6.0 allowable output low current (total) i ol output pins except port 6, scl, and sda ? ? 20.0 ma port 6, scl, and sda ? ? 40.0 allowable output high current (per pin) ? ?i oh ? all output pins ? ? 2.0 ma allowable output high current (total) ? ? i oh ? all output pins ? ? 20.0 ma section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 381 of 472 rej09b0160-0200 20.2.3 ac characteristics table 20.3 ac characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure system clock oscillation frequency f osc osc1, osc2 4.0 ? 18.0 mhz t cyc 1 ? 64 t osc figure 20.1 * system clock ( ) cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock high width t cph osc1 25.0 ? ? ns figure 20.1 external clock low width t cpl osc1 25.0 ? ? ns external clock rise time t cpr osc1 ? ? 10.0 ns external clock fall time t cpf osc1 ? ? 10.0 ns section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 382 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit reference figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 20.2 in active mode and sleep mode operation 200 ? ? ns input pin high width t ih nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc figure 20.3 input pin low width t il nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc notes: * determined by ma2, ma1, ma0, sa1, and sa 0 of system control register 2 (syscr2). section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 383 of 472 rej09b0160-0200 table 20.4 i 2 c bus interface timing v cc = 3.6 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit reference figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 20.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc + 20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf ? ? 300 ns section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 384 of 472 rej09b0160-0200 table 20.5 serial communicati on interface (sci) timing v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure asynchro- nous t scyc sck3 4 ? ? t cyc input clock cycle clocked synchro- nous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc figure 20.5 figure 20.6 transmit data delay time (clocked synchronous) t txd txd ? ? 1 t cyc figure 20.6 receive data setup time (clocked synchronous) t rxs rxd 55.5 ? ? ns receive data hold time (clocked synchronous) t rxh rxd 55.5 ? ? ns section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 385 of 472 rej09b0160-0200 20.2.4 a/d converter characteristics table 20.6 a/d convert er characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure analog power supply voltage av cc av cc 3.0 v cc 3.6 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 3.3 v f osc = 18 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.0 to 3.6 v 134 ? ? t cyc nonlinearity error ? ? 5.5 lsb offset error ? ? 5.5 lsb full-scale error ? ? 5.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 6.0 lsb conversion time (single mode) av cc = 3.0 to 3.6 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 386 of 472 rej09b0160-0200 notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 20.2.5 watchdog timer characteristics table 20.7 watchdog ti mer characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected. section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 387 of 472 rej09b0160-0200 20.2.6 flash memory characteristics table 20.8 flash memory characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7 200 ms erase time (per block) * 1 * 3 * 6 t e ? 100 1200 ms reprogramming count n wec 1000 10000 ? times programming wait time after swe bit setting * 1 x 1 ? ? s wait time after psu bit setting * 1 y 50 ? ? s wait time after p bit setting z1 1 n 6 28 30 32 s * 1 * 4 z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after p bit clear * 1 5 ? ? s wait time after psu bit clear * 1 5 ? ? s wait time after pv bit setting * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after pv bit clear * 1 2 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 388 of 472 rej09b0160-0200 values item symbol test condition min. typ. max. unit erasing wait time after swe bit setting * 1 x 1 ? ? s wait time after esu bit setting * 1 y 100 ? ? s wait time after e bit setting * 1 * 6 z 10 ? 100 ms wait time after e bit clear * 1 10 ? ? s wait time after esu bit clear * 1 10 ? ? s wait time after ev bit setting * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after ev bit clear * 1 4 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time se ttings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indicate s the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (i ndicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. programming time maximum value (t p (max.)) = wait time a fter p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) acco rding to the actual se t values of z1, z2, and z3, so that it does not exceed the programming time maximum value (t p (max.)). the wait time after p bit setting (z1, z2) s hould be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erase time maximum value (t e (max.)) = wait time after e bit setting (z) maximum erase count (n) 7. set the maximum erase count (n) according to the actual set value of (z), so that it does not exceed the erase time maximum value (t e (max.)). section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 389 of 472 rej09b0160-0200 20.3 electrical characteristics (mask-rom version) 20.3.1 power supply voltage and operating ranges (1) power supply voltage and oscillation frequency range 4.0 18.0 3.0 3.6 vcc(v) osc(mhz) 32.768 3.0 3.6 vcc(v) w(khz) av cc = 3.0 to 3.6v av cc = 3.0 to 3.6v all operating modes active mode sleep mode section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 390 of 472 rej09b0160-0200 (2) power supply voltage and operating frequency range 16.384 8.192 4.096 3.0 3.6 vcc(v) w(khz) 4.0 18.0 3.0 3.6 vcc(v) osc(mhz) 78.125 2250 3.0 3.6 vcc(v) (khz) av cc = 3.0 to 3.6v av cc = 3.0 to 3.6v av cc = 3.0 to 3.6v active mode sleep mode (when ma2 in syscr2 = 0) (when ma2 in syscr2 = 1) subsleep mode subactive mode active mode sleep mode (3) analog power supply voltage and a/ d converter accuracy guarantee range 4.0 18.0 3.0 3.6 avcc(v) osc(mhz) v cc = 3.0 to 3.6v active mode sleep mode section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 391 of 472 rej09b0160-0200 20.3.2 dc characteristics table 20.9 dc characteristics (1) v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, v cc 0.8 ? v cc + 0.3 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv rxd, rxd_2 scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37 v cc 0.7 ? v cc + 0.3 v p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87 pb0 to pb7 v cc 0.7 ? av cc + 0.3 v note: connect the test pin to vss. section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 392 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes osc1 v cc ? 0.5 ? v cc + 0.3 v input high voltage v ih input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmib1, tmriv, ?0.3 ? v cc 0.2 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, sck3, sck3_2, trgv rxd, rxd_2, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?0.3 ? v cc 0.3 v p50 to p57, p60 to p67,. p70 to p72, p74 to p76, p85 to p87 pb0 to pb7 ?0.3 ? v cc 0.3 v osc1 ?0.3 ? 0.5 v output high voltage v oh p10 to p12, p14 to p17, p20 to p24, p30 to p37, ?i oh = 2.0 ma v cc ? 0.5 ? ? v p50 to p55, p60 to p67, p70 to p72, p74 to p76, p85 to p87 p56, p57 ?i oh = 0.1 ma v cc ? 2.0 ? ? v section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 393 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes output low voltage v ol p10 to p12, p14 to p17, p20 to p24, p30 to p37, i ol = 1.6 ma ? ? 0.6 v p50 to p57, p70 to p72, p74 to p76, p85 to p87 i ol = 0.4 ma ? ? 0.4 p60 to p67 i ol = 10.0 ma ? ? 1.0 v i ol = 1.6 ma ? ? 0.4 scl, sda i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4 input/ output leakage current | i il | osc1, tmib1, nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, rxd, sck3, rxd_2, sck3_2, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p24, p30 to p37, p50 to p57, p60 to p67, p70 to p72, p74 to p76, p85 to p87, v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a pull-up mos current ?i p p10 to p12, p14 to p17, p50 p55 v cc = 3.3 v, v in = 0.0 v 33.0 ? 165.0 a pull-up resistor r p res 60.0 150.0 ? k ? input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 394 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes i ope1 v cc active mode 1 v cc = 3.3 v, f osc = 18 mhz ? 21.0 28.0 ma * active mode current consump- tion active mode 1 v cc = 3.3 v, f osc = 10 mhz ? 11.6 ? * reference value i ope2 v cc active mode 2 v cc = 3.3 v, f osc = 18 mhz ? 1.4 2.8 ma * active mode 2 v cc = 3.3 v, f osc = 10 mhz ? 1.2 ? * reference value i sleep1 v cc sleep mode 1 v cc = 3.3 v, f osc = 18 mhz ? 16.5 21.0 ma * sleep mode current consump- tion sleep mode 1 v cc = 3.3 v, f osc = 10 mhz ? 9.0 ? * reference value i sleep2 v cc sleep mode 2 v cc = 3.3 v, f osc = 18 mhz ? 1.3 2.5 ma * sleep mode 2 v cc = 3.3v, f osc = 10 mhz ? 1.1 ? * reference value i sub v cc v cc = 3.3 v 32-khz crystal resonator ( sub = w /2) ? 35.0 60.0 a * subactive mode current consump- tion v cc = 3.3 v 32-khz crystal resonator ( sub = w /8) ? 20.0 ? * reference value i subsp1 v cc subsleep mode 1 v cc = 3.3 v 32-khz crystal resonator ( sub = w /2) ? 20.0 40.0 a * subsleep mode current consump- tion i subsp2 v cc subsleep mode 2 v cc = 3.3 v 32-khz crystal resonator not used ? ? 5.0 a * section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 395 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit notes standby mode current consump- tion i stby v cc 32-khz crystal resonator not used ? ? 5.0 a * ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during current consumption meas urement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator active mode 2 operates ( osc/64) subclock: pin x1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc/64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode 1 v cc only timers operate v cc subclock resonator: crystal subsleep mode 2 cpu and timers both stop main clock: ceramic or crystal resonator subclock: pin x1 = v ss standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x1 = v ss section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 396 of 472 rej09b0160-0200 table 20.9 dc characteristics (2) v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit allowable output low current (per pin) i ol output pins except port 6, scl, and sda ? ? 2.0 ma port 6 ? ? 10.0 scl, sda ? ? 6.0 allowable output low current (total) i ol output pins except port 6, scl, and sda ? ? 20.0 ma port 6, scl, and sda ? ? 40.0 allowable output high current (per pin) ? ?i oh ? all output pins ? ? 2.0 ma allowable output high current (total) ? ? i oh ? all output pins ? ? 20.0 ma section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 397 of 472 rej09b0160-0200 20.3.3 ac characteristics table 20.10 ac characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure system clock oscillation frequency f osc osc1, osc2 4.0 ? 18.0 mhz t cyc 1 ? 64 t osc system clock ( ) cycle time ? ? 12.8 s figure 20.1 * subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock high width t cph osc1 25.0 ? ? ns figure 20.1 external clock low width t cpl osc1 25.0 ? ? ns external clock rise time t cpr osc1 ? ? 10.0 ns external clock fall time t cpf osc1 ? ? 10.0 ns section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 398 of 472 rej09b0160-0200 values item symbol applicable pins test condition min. typ. max. unit reference figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 20.2 in active mode and sleep mode operation 200 ? ? ns input pin high width t ih nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc figure 20.3 input pin low width t il nmi , tmib1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1 2 ? ? t cyc t subcyc notes: * determined by ma2, ma1, ma0, sa1, and sa 0 of system control register 2 (syscr2). section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 399 of 472 rej09b0160-0200 table 20.11 i 2 c bus interface timing v cc = 3.0 v to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit reference figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 20.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc + 20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf ? ? 300 ns section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 400 of 472 rej09b0160-0200 table 20.12 serial communicati on interface (sci) timing v cc = 3.0 v to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure asynchro- nous t scyc sck3 4 ? ? t cyc input clock cycle clocked synchronous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc figure 20.5 figure 20.6 transmit data delay time (clocked sycronous) t txd txd ? ? 1 t cyc figure 20.6 receive data setup time (clocked synchronous) t rxs rxd 55.5 ? ? ns receive data hold time (clocked synchronous) t rxh rxd 55.5 ? ? ns section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 401 of 472 rej09b0160-0200 20.3.4 a/d converter characteristics table 20.13 a/d converter characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure analog power supply voltage av cc av cc 3.0 v cc 3.6 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 3.3 v f osc = 18 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.0 to 3.6 v 134 ? ? t cyc nonlinearity error ? ? 5.5 lsb offset error ? ? 5.5 lsb full-scale error ? ? 5.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 6.0 lsb conversion time (single mode) av cc = 3.0 to 3.6 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 402 of 472 rej09b0160-0200 notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 20.3.5 watchdog timer characteristics table 20.14 watchdog timer characteristics v cc = 3.0 to 3.6 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit reference figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected. section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 403 of 472 rej09b0160-0200 20.4 operation timing t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 20.1 system clock input timing t rel v il res t rel v il v cc 0.7 v cc osc1 figure 20.2 res low width timing v ih v il t il nmi irq0 to irq3 wkp0 to wkp5 adtrg ftioa0 to ftiod0, ftioa1 to ftiod1, tmciv, tmriv trgv, tmib1 t ih figure 20.3 input timing section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 404 of 472 rej09b0160-0200 scl v ih v il t stah t buf p * s * t sf t sr t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the following: s: start condition p: stop condition sr: retransmission start condition figure 20.4 i 2 c bus interface input/output timing t scyc t sckw sck3 figure 20.5 sck3 input clock timing section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 405 of 472 rej09b0160-0200 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol * sck3 txd (transmit data) rxd (receive data) note: * output timing reference levels output high: output low: load conditions are shown in figure 20.7. v = 2.0 v v = 0.8 v oh ol figure 20.6 sci input/output ti ming in clocked synchronous mode section 20 electric al characteristics rev. 2.00 sep. 23, 2005 page 406 of 472 rej09b0160-0200 20.5 output load condition v cc 2.4 k ? 12 k ? 30 pf lsi output pin figure 20.7 output load circuit appendix rev. 2.00 sep. 23, 2005 page 407 of 472 rej09b0160-0200 appendix a instruction set a.1 instruction list ? condition code symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (addr ess register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the op erand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides logical exclusive or of the operands on both sides appendix rev. 2.00 sep. 23, 2005 page 408 of 472 rej09b0160-0200 symbol description ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7). ? condition code notation (cont) symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction ? varies depending on conditions, described in notes appendix rev. 2.00 sep. 23, 2005 page 409 of 472 rej09b0160-0200 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov appendix rev. 2.00 sep. 23, 2005 page 410 of 472 rej09b0160-0200 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe appendix rev. 2.00 sep. 23, 2005 page 411 of 472 rej09b0160-0200 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? * (1) (1) (2) (2) ? ? ? ? ? ? 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) ? ? ? (3) (3) ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec appendix rev. 2.00 sep. 23, 2005 page 412 of 472 rej09b0160-0200 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? ? ? * ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? (7) (7) (7) (7) ? ? (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp appendix rev. 2.00 sep. 23, 2005 page 413 of 472 rej09b0160-0200 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( appendix rev. 2.00 sep. 23, 2005 page 414 of 472 rej09b0160-0200 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 ? #xx:8 rd8 rd8 ? rs8 rd8 rd16 ? #xx:16 rd16 rd16 ? rs16 rd16 erd32 ? #xx:32 erd32 erd32 ? ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not appendix rev. 2.00 sep. 23, 2005 page 415 of 472 rej09b0160-0200 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr appendix rev. 2.00 sep. 23, 2005 page 416 of 472 rej09b0160-0200 5. bit-manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bset bclr bnot btst bld appendix rev. 2.00 sep. 23, 2005 page 417 of 472 rej09b0160-0200 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bist bst band biand bor bior bxor bixor appendix rev. 2.00 sep. 23, 2005 page 418 of 472 rej09b0160-0200 6. branching instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 if condition is true then pc pc+d else next; branch condition bcc appendix rev. 2.00 sep. 23, 2005 page 419 of 472 rej09b0160-0200 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc ern pc @?sp pc aa:24 pc @?sp pc @aa:8 pc @sp+ ? ? ? ? ? ? ? ? ? 2 2 4 4 2 4 2 2 2 ? ? ? ? ? ? ? ? ? 4 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts appendix rev. 2.00 sep. 23, 2005 page 420 of 472 rej09b0160-0200 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation pc @?sp ccr @?sp appendix rev. 2.00 sep. 23, 2005 page 421 of 472 rej09b0160-0200 8. block transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? eepmov. b eepmov. w operation if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next if r4 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next ? ? 4 4 ? ? 8+ 4n * 2 normal advanced ? ? ? ? ? ? ? ? ? ?8+ 4n * 2 eepmov notes: 1. the number of states in cases wher e the instruction code and its operands are located in on-chip memory is shown here. for ot her cases see section a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for executi on of an instruction t hat transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0. appendix rev. 2.00 sep. 23, 2005 page 422 of 472 rej09b0160-0200 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b appendix rev. 2.00 sep. 23, 2005 page 423 of 472 rej09b0160-0200 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg appendix rev. 2.00 sep. 23, 2005 page 424 of 472 rej09b0160-0200 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc appendix rev. 2.00 sep. 23, 2005 page 425 of 472 rej09b0160-0200 a.3 number of execution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instructio n execution are shown belo w. table a.4 shows the number of cycles of each type occurring in each instruction, such as in struction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n ? examples when instruction is fetched from on-chi p rom, and an on-chip ram is accessed. a. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. b. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 appendix rev. 2.00 sep. 23, 2005 page 426 of 472 rej09b0160-0200 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip me mory on-chip peripheral module instruction fetch s i 2 ? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m 2 or 3 * internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 19.1, register addresses (address order). appendix rev. 2.00 sep. 23, 2005 page 427 of 472 rej09b0160-0200 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 appendix rev. 2.00 sep. 23, 2005 page 428 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 appendix rev. 2.00 sep. 23, 2005 page 429 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 appendix rev. 2.00 sep. 23, 2005 page 430 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 1 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 appendix rev. 2.00 sep. 23, 2005 page 431 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 duvxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1 inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 2 1 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 2 1 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 appendix rev. 2.00 sep. 23, 2005 page 432 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) 2 3 2 1 1 2 4 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 2 appendix rev. 2.00 sep. 23, 2005 page 433 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs,@aa:16 * 2 2 1 mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 appendix rev. 2.00 sep. 23, 2005 page 434 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1 rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 appendix rev. 2.00 sep. 23, 2005 page 435 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1 subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 4 appendix rev. 2.00 sep. 23, 2005 page 436 of 472 rej09b0160-0200 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n: specified value in r4l and r4. the source and destination operands are accessed n+1 times respectively. 2. cannot be used in this lsi. appendix rev. 2.00 sep. 23, 2005 page 437 of 472 rej09b0160-0200 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl ? ? bwl wl b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? b ? ? #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 ? bwl ? ? bwl bwl b l bwl b bw bwl wl bwl bwl bwl b ? ? ? ? ? ? b b ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw functions instructions appendix rev. 2.00 sep. 23, 2005 page 438 of 472 rej09b0160-0200 appendix b i/o port block diagrams b.1 i/o port block diagrams res goes low in a reset, and sby goes low at reset and in standby mode. pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq trgv internal data bus pull-up mos [legend] figure b.1 port 1 block diagram (p17) appendix rev. 2.00 sep. 23, 2005 page 439 of 472 rej09b0160-0200 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq internal data bus pull-up mos [legend] figure b.2 port 1 block diagram (p14, p16) appendix rev. 2.00 sep. 23, 2005 page 440 of 472 rej09b0160-0200 pdr pucr pmr pcr sby res [legend] pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register internal data bus pull-up mos irq tmib1 figure b.3 port 1 block diagram (p15) appendix rev. 2.00 sep. 23, 2005 page 441 of 472 rej09b0160-0200 pdr pucr pcr sby res [legend] pucr: pdr: pcr: port pull-up control register port data register port control register internal data bus pull-up mos figure b.4 port 1 block diagram (p12) appendix rev. 2.00 sep. 23, 2005 page 442 of 472 rej09b0160-0200 pdr pucr pmr pcr sby res pwm 14-bit pwm internal data bus pull-up mos [legend] pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register figure b.5 port 2 block diagram (p11) appendix rev. 2.00 sep. 23, 2005 page 443 of 472 rej09b0160-0200 pdr pucr pmr pcr sby res pucr: pmr: pdr: pcr: [legend] port pull-up control register port mode register port data register port control register internal data bus pull-up mos tmow rtc figure b.6 port 1 block diagram (p10) appendix rev. 2.00 sep. 23, 2005 page 444 of 472 rej09b0160-0200 pdr pmr pcr sby pmr: pdr: pcr: [legend] port mode register port data register port control register internal data bus figure b.7 port 2 block diagram (p24, p23) appendix rev. 2.00 sep. 23, 2005 page 445 of 472 rej09b0160-0200 pdr pmr pcr sby txd sci3 pmr: pdr: pcr: [legend] port mode register port data register port control register internal data bus figure b.8 port 2 block diagram (p22) appendix rev. 2.00 sep. 23, 2005 page 446 of 472 rej09b0160-0200 pdr pcr sby pdr: port data register pcr: port control register re internal data bus rxd sci3 [legend] figure b.9 port 2 block diagram (p21) appendix rev. 2.00 sep. 23, 2005 page 447 of 472 rej09b0160-0200 pdr pcr sby pdr: port data register pcr: port control register sckie internal data bus scki sci3 sckoe scko [legend] figure b.10 port 2 block diagram (p20) appendix rev. 2.00 sep. 23, 2005 page 448 of 472 rej09b0160-0200 pdr pcr sby [legend] pdr: pcr: port data register port control register internal data bus figure b.11 port 3 block diagram (p37 to p30) appendix rev. 2.00 sep. 23, 2005 page 449 of 472 rej09b0160-0200 pdr pmr pcr sby ice sdao/sclo sdai/scli iic2 pmr: pdr: pcr: port mode register port data register port control register internal data bus [legend] figure b.12 port 5 block diagram (p57, p56) appendix rev. 2.00 sep. 23, 2005 page 450 of 472 rej09b0160-0200 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus adtrg pull-up mos [legend] figure b.13 port 5 block diagram (p55) appendix rev. 2.00 sep. 23, 2005 page 451 of 472 rej09b0160-0200 pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus pull-up mos [legend] figure b.14 port 5 block diagram (p54 to p50) appendix rev. 2.00 sep. 23, 2005 page 452 of 472 rej09b0160-0200 pdr pcr sby pdr: pcr: port data register port control register [legend] ftioa to ftiod output control signals a to d timer z internal data bus figure b.15 port 6 block diagram (p67 to p60) appendix rev. 2.00 sep. 23, 2005 page 453 of 472 rej09b0160-0200 pdr pcr sby os3 os2 os1 os0 tmov pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.16 port 7 block diagram (p76) appendix rev. 2.00 sep. 23, 2005 page 454 of 472 rej09b0160-0200 pdr pcr sby tmciv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.17 port 7 block diagram (p75) appendix rev. 2.00 sep. 23, 2005 page 455 of 472 rej09b0160-0200 pdr pcr sby tmriv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.18 port 7 block diagram (p74) appendix rev. 2.00 sep. 23, 2005 page 456 of 472 rej09b0160-0200 pdr pmr pcr sby [legend] pmr: pdr: pcr: port mode register port data register port control register internal data bus txd sci3_2 figure b.19 port 7 block diagram (p72) appendix rev. 2.00 sep. 23, 2005 page 457 of 472 rej09b0160-0200 pdr pcr sby re rxd sci3_2 [legend] pdr: pcr: port data register port control register internal data bus figure b.20 port 7 block diagram (p71) pdr pcr sby sckie scki sci3_2 sckoe scko [legend] pdr: pcr: port data register port control register internal data bus figure b.21 port 7 block diagram (p70) appendix rev. 2.00 sep. 23, 2005 page 458 of 472 rej09b0160-0200 pdr pcr sby pdr: port data register pcr: port control register internal data bus [legend] figure b.22 port 8 block diagram (p87 to p85) appendix rev. 2.00 sep. 23, 2005 page 459 of 472 rej09b0160-0200 dec a/d converter internal data bus v in ch3 to ch0 figure b.23 port b block diagram (pb7 to pb0) appendix rev. 2.00 sep. 23, 2005 page 460 of 472 rej09b0160-0200 b.2 port states in each operating state port reset sleep subsleep standby subactive active p17 to p14, p12 to p10 high impedance retained retained high impedance * functioning functioning p24 to p20 high impedance retained retained high impedance functioning functioning p37 to p30 high impedance retained retained high impedance functioning functioning p57 to p50 high impedance retained retained high impedance * functioning functioning p67 to p60 high impedance retained retained high impedance functioning functioning p76 to p74, p72 to p70 high impedance retained retained high impedance functioning functioning p87 to p85 high impedance retained retained high impedance functioning functioning pb7 to pb0 high impedance high impedance high impedance high impedance high impedance high impedance notes: * high level output when the pul l-up mos is in on state. appendix rev. 2.00 sep. 23, 2005 page 461 of 472 rej09b0160-0200 appendix c product code lineup product classification product code model marking package code hd64f36087h df36087h qfp-64 (fp-64a) h8/36087 flash memory version standard product hd64f36087fp df36087fp lqfp-64 (fp-64e) HD64336087h d336087( *** )h qfp-64 (fp-64a) mask rom version standard product HD64336087fp d336087( *** )fp lqfp-64 (fp-64e) hd64336086h d336086( *** )h qfp-64 (fp-64a) h8/36086 mask rom version standard product hd64336086fp d336086( *** )fp lqfp-64 (fp-64e) hd64336085h d336085( *** )h qfp-64 (fp-64a) h8/36085 mask rom version standard product hd64336085fp d336085( *** )fp lqfp-64 (fp-64e) hd64336084h d336084( *** )h qfp-64 (fp-64a) h8/36084 mask rom version standard product hd64336084fp d336084( *** )fp lqfp-64 (fp-64e) hd64336083h d336083( *** )h qfp-64 (fp-64a) h8/36083 mask rom version standard product hd64336083fp d336083( *** )fp lqfp-64 (fp-64e) hd64336082h d336082( *** )h qfp-64 (fp-64a) h8/36082 mask rom version standard product hd64336082fp d336082( *** )fp lqfp-64 (fp-64e) [legend] ( *** ): rom code appendix rev. 2.00 sep. 23, 2005 page 462 of 472 rej09b0160-0200 appendix d package dimensions the package dimensions that are shown in the renesas semiconductor packages data book have priority. appendix rev. 2.00 sep. 23, 2005 page 463 of 472 rej09b0160-0200 1.0 11.8 12.0 12.2 1.45 10 reference symbol dimension in millimeters min nom max 0.3 0.5 0.7 previous code jeita package code renesas code fp-64e/fp-64ev 10 mass[typ.] 0.4g h l e c a d e a h a b b c x y z z l 2 d e 1 p 1 1 d e 1 12.2 12.0 11.8 1.70 0.12 0.17 0.22 0.17 0.22 0.27 0.00 0.20 0.15 0.10 0.20 0 8 0.5 0.10 0.08 1.25 1.25 p-lqfp64-10x10-0.50 plqp0064kc-a f y m x 33 48 32 49 16 17 1 64 d e d e p * 3 * 2 * 1 index mark d h e h z z b detail f 1 1 2 c l a l a a 1 1 p terminal cross section b c b c e note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. figure d.1 fp-64e package dimensions appendix rev. 2.00 sep. 23, 2005 page 464 of 472 rej09b0160-0200 prqp0064gb-a p-qfp64-14x14-0.80 0.8 1.0 1.0 0.15 0.10 8 0 0.25 0.10 0.15 0.35 0.00 0.45 0.37 0.29 0.22 0.17 0.12 3.05 16.9 17.2 17.5 d 1 e d 1 1 p 1 e d 2 l z z y x c b b a h a e a c e l h 1.2g mass[typ.] fp-64a/fp-64av renesas code jeita package code previous code 1.1 0.8 0.5 max nom min dimension in millimeters symbol reference 14 2.70 17.5 17.2 16.9 1.6 14 note) 1. dimensions"*1"and"*2" do not include mold flash 2. dimension"*3"does not include trim offset. * 1 * 2 * 3 p e d e d xm y f 64 1 17 16 49 48 32 33 z z d h e h b 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b e figure d.2 fp-64a package dimensions rev. 2.00 sep. 23, 2005 page 465 of 354 rej09b0160-0200 main revisions and add itions in this edition item page revision (s ee manual for details) preface vi, vii when using the on-chip emulator (e7, e8) for h8/36087 program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 3. area h'd000 to h'dfff is us ed by the e7 or e8, and is not available to the user. 5. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 6. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode). 7. use channel 1 of the sci3 (p21/rxd, p22/txd) in on- board programming mode by boot mode. note has been deleted. bit bit name description 3 nesel noise elimination sampling frequency select the subclock pulse generator generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 18 mhz, clear nesel to 0. section 6 power-down modes 6.1.1 system control register 1 (syscr1) 75 section 8 ram 107 note: * when the e7 or e8 is used, area h'f780 to h'fb7f must not be accessed. rev. 2.00 sep. 23, 2005 page 466 of 354 rej09b0160-0200 item page revision (s ee manual for details) bit bit name description 0 sync timer synchronization 0: tcnt_1 and tcnt_0 operate as a different timer 1: tcnt_1 and tcnt_0 are synchronized tcnt_1 and tcnt_0 can be pre-set or cleared synchronously section 13 timer z 13.3.2 timer mode register (tmdr) 181 13.4.4 synchronous operation 208 figure 13.20 shows an example of synchronous operation. in this example, synchronous operation has been selected, ftiob0 and ftiob1 have been designated for pwm mode, gra_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. in addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. two-phase pwm waveforms are output from pins ftiob0 and ftiob1. 13.4.9 timer z output timing figure 13.44 example of output disable timing of timer z by writing to toer 237 timer z output pin timer output address bus toer address t 1 t 2 i/o port timer z output i/o port figure 13.45 example of output disable timing of timer z by external trigger 237 toer n timer z output pin timer z output timer z output i/o port i/o port h'ff bit bit name description 4 tcsrwe timer control/status register wd write enable section 14 watchdog timer 14.2.1 timer control/status register wd (tcsrwd) 252 rev. 2.00 sep. 23, 2005 page 467 of 354 rej09b0160-0200 item page revision (s ee manual for details) bit bit name description 3 stop [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in sar [clearing condition] ? when 0 is written in stop after reading stop = 1 section 17 i 2 c bus interface 2 (iic2) 17.3.5 i 2 c bus status register (icsr) 320 17.7 usage notes 343 added section 18 a/d converter 18.3.1 a/d data registers a to d (addra to addrd) 348 therefore byte access to addr should be done by reading the upper byte first then the lower one. word access is also possible. addr is initialized to h'0000. mode res pin internal state active mode 1 operates active mode 2 v cc operates ( osc/64) sleep mode 1 only timers operate sleep mode 2 v cc only timers operate ( osc/64) section 20 electrical characteristics 20.2.2 dc characteristics table 20.2 dc characteristics (1) 379 rev. 2.00 sep. 23, 2005 page 468 of 354 rej09b0160-0200 item page revision (s ee manual for details) mode res pin internal state active mode 1 operates active mode 2 v cc operates ( osc/64) sleep mode 1 only timers operate sleep mode 2 v cc only timers operate ( osc/64) 20.3.2 dc characteristics table 20.9 dc characteristics (1) 395 20.3.2 dc characteristics 20.3.3 ac characteristics 20.3.4 a/d converter characteristics 20.3.5 watchdog timer characteristics 391 to 402 preliminary has been deleted. appendix d.1 package dimensions 463, 464 swapped with new ones. rev. 2.00 sep. 23, 2005 page 469 of 472 rej09b0160-0200 index numerics 14-bit pwm ............................................ 257 register se ttings.................................. 259 waveform output................................ 260 a a/d converter ......................................... 345 sample-and-hold circuit...................... 352 scan mode........................................... 351 single mode ........................................ 351 address break ........................................... 61 addressing modes..................................... 30 absolute address................................... 31 immediate ............................................. 32 memory indirect ................................... 32 program-counter relative ...................... 32 register direct....................................... 31 register indirect.................................... 31 register indirect w ith displacement...... 31 register indirect with post-increment... 31 register indirect with pre-decrement.... 31 c clock pulse generators.............................. 67 prescaler s ............................................ 71 prescaler w........................................... 71 subclock generator ............................... 70 system clock generator......................... 68 condition fi eld.......................................... 29 condition-code register (ccr)................. 14 cpu ............................................................ 9 e effective address....................................... 34 effective address extension....................... 29 exception handling ................................... 45 reset exception handling ...................... 55 stack status ........................................... 58 trap instruction..................................... 45 f flash memory ........................................... 87 boot mode............................................. 94 boot program ........................................ 93 erase/erase-verify ............................... 101 erasing units ......................................... 87 error protection................................... 103 hardware protection............................ 103 power-down st ates .............................. 104 program/program-verify ....................... 98 programmer mode............................... 104 programming units................................ 87 programming/erasing in user program mode...................................................... 96 software protection............................. 103 g general registers ....................................... 13 i i/o ports .................................................. 109 i/o port block diagrams ...................... 438 i 2 c bus format ......................................... 324 i 2 c bus interface 2 (iic2)........................ 307 acknowledge ...................................... 325 bit synchronous circuit ....................... 342 clock synchronous serial format......... 333 noise canceler..................................... 336 rev. 2.00 sep. 23, 2005 page 470 of 472 rej09b0160-0200 slave address ...................................... 325 start cond ition .................................... 325 stop condition..................................... 325 transfer rate........................................ 312 instruction set ........................................... 19 arithmetic operations instructions........ 21 bit manipulation instructions................ 24 block data transfer instructions ............ 28 branch instructions ............................... 26 data transfer instructions...................... 20 logic operations instructions................ 23 shift instructions................................... 23 system control instructions................... 27 interrupt internal interrupts ................................. 57 interrupt response time ................... 57, 58 irq3 to irq0 interrupts ....................... 55 nmi interrupt........................................ 55 wkp5 to wkp0 interrupts ................... 56 interrupt mask bit ..................................... 15 l large current ports...................................... 2 m memory map ............................................ 10 module standby function .......................... 85 o on-board programming modes................. 93 operation field.......................................... 29 p package....................................................... 2 package dimensions................................ 462 pin arrangement .......................................... 4 power-down modes................................... 73 sleep mode............................................ 82 standby mode ....................................... 82 subactive mode..................................... 83 subsleep mode ...................................... 82 product code lineup ................................ 461 program counter (pc) ............................... 14 r realtime cloc k (rtc) ............................. 141 data reading procedure ....................... 151 initial setting procedure ...................... 150 registers abrkcr...................... 62, 361, 367, 371 abrksr ...................... 64, 361, 367, 371 adcr ......................... 350, 361, 367, 371 adcsr ....................... 349, 361, 367, 371 addra ...................... 348, 361, 366, 371 addrb ...................... 348, 361, 366, 371 addrc ...................... 348, 361, 367, 371 addrd ...................... 348, 361, 367, 371 barh ........................... 64, 361, 367, 371 barl............................ 64, 361, 367, 371 bdrh ........................... 64, 361, 367, 371 bdrl............................ 64, 362, 367, 371 brr ............................ 271, 361, 366, 371 ebr1............................. 91, 360, 366, 370 fenr ............................ 92, 360, 366, 370 flmcr1....................... 89, 360, 366, 370 flmcr2....................... 90, 360, 366, 370 flpwcr ...................... 92, 360, 366, 370 gra............................ 188, 358, 364, 369 grb ............................ 188, 358, 364, 369 grc ............................ 188, 358, 364, 369 grd............................ 188, 358, 364, 369 iccr1 ......................... 311, 360, 365, 370 iccr2 ......................... 313, 360, 365, 370 icdrr ........................ 323, 360, 366, 370 rev. 2.00 sep. 23, 2005 page 471 of 472 rej09b0160-0200 icdrs ................................................ 323 icdrt ........................ 323, 360, 366, 370 icier.......................... 317, 360, 365, 370 icmr.......................... 315, 360, 365, 370 icsr ........................... 319, 360, 365, 370 iegr1........................... 48, 363, 368, 372 iegr2........................... 49, 363, 368, 372 ienr1........................... 50, 363, 368, 372 ienr2........................... 51, 363, 368, 372 irr1 ............................. 51, 363, 368, 372 irr2 ............................. 53, 363, 368, 372 iwpr ............................ 53, 363, 368, 372 mstcr1....................... 77, 363, 368, 372 mstcr2....................... 78, 363, 368, 372 pcr1........................... 111, 362, 368, 372 pcr2........................... 115, 362, 368, 372 pcr3........................... 119, 362, 368, 372 pcr5........................... 124, 362, 368, 372 pcr6........................... 129, 362, 368, 372 pcr7........................... 134, 362, 368, 372 pcr8........................... 137, 362, 368, 372 pdr1 .......................... 111, 362, 367, 372 pdr2 .......................... 116, 362, 367, 372 pdr3 .......................... 119, 362, 367, 372 pdr5 .......................... 124, 362, 367, 372 pdr6 .......................... 129, 362, 367, 372 pdr7 .......................... 135, 362, 367, 372 pdr8 .......................... 138, 362, 367, 372 pdrb.......................... 139, 362, 367, 372 pmr1.......................... 110, 362, 368, 372 pmr3.......................... 116, 362, 368, 372 pmr5.......................... 123, 362, 368, 372 pocr.......................... 195, 358, 364, 369 pucr1........................ 112, 362, 367, 372 pucr5........................ 125, 362, 367, 372 pwcr......................... 258, 361, 367, 371 pwdrl ...................... 259, 361, 367, 371 pwdru...................... 259, 361, 367, 371 rdr............................ 265, 361, 366, 371 rhrdr ...................... 145, 359, 365, 370 rmindr .................... 144, 359, 365, 370 rsecdr..................... 143, 359, 365, 370 rsr..................................................... 265 rtccr1 ..................... 147, 359, 365, 370 rtccr2 ..................... 148, 359, 365, 370 rtccsr ..................... 149, 359, 365, 370 rwkdr...................... 146, 359, 365, 370 sar............................. 322, 360, 366, 370 scr3........................... 267, 361, 366, 371 smr ............................ 266, 361, 366, 371 ssr ............................. 269, 361, 366, 371 syscr1........................ 74, 363, 368, 372 syscr2........................ 76, 363, 368, 372 tcb1........................... 155, 360, 366, 370 tcnt .......................... 187, 358, 364, 369 tcntv ....................... 161, 360, 366, 371 tcora....................... 162, 360, 366, 371 tcorb ....................... 162, 360, 366, 371 tcr............................. 189, 358, 364, 369 tcrv0........................ 162, 360, 366, 371 tcrv1........................ 165, 360, 366, 371 tcsrv........................ 164, 360, 366, 371 tcsrwd.................... 252, 361, 367, 371 tcwd......................... 253, 361, 367, 371 tdr ............................ 265, 361, 366, 371 tfcr .......................... 182, 359, 365, 369 tier............................ 194, 358, 364, 369 tiora ........................ 190, 358, 364, 369 tiorc ........................ 191, 358, 364, 369 tlb1................................................... 155 tmb1.......................... 154, 360, 366, 370 tmdr......................... 180, 359, 365, 369 tmwd........................ 254, 361, 367, 371 tocr.......................... 186, 359, 365, 369 toer .......................... 185, 359, 365, 369 tpmr.......................... 181, 359, 365, 369 tsr ............................. 192, 358, 364, 369 tstr........................... 180, 359, 365, 369 register field............................................. 29 rev. 2.00 sep. 23, 2005 page 472 of 472 rej09b0160-0200 s serial communication interface 3 (sci3) ..................................................... 261 asynchronous mode ........................... 280 bit rate ................................................ 271 break .................................................. 305 clocked synchronous mode................ 288 framing error...................................... 284 mark state ........................................... 305 multiprocessor communication function............................................... 296 overrun error ...................................... 284 parity error.......................................... 284 stack pointer (sp)..................................... 14 t timer b1................................................. 153 auto-reload timer operation ............... 156 event counter operation...................... 156 interval timer operation....................... 156 timer v................................................... 159 timer z ................................................... 173 buffer operation.................................. 229 complementary pwm mode .............. 219 input capture function ......................... 204 pwm mode ......................................... 209 reset synchronous pwm mode .......... 215 synchronous operation........................ 207 waveform output by compare match.. 201 v vector address........................................... 46 w watchdog timer....................................... 251 renesas 16-bit single-chip microcomputer hardware manual h8/36087 group publication date: rev.1.00, jun. 03, 2004 rev.2.00, sep. 23, 2005 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2005. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> 2-796-3115, fax: <82> 2-796-2145 renesas technology malaysia sdn. bhd. unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 3.0 h8/36087 group hardware manual |
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